soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK

Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build.  The .S files
are mostly duplicated code from the old cache_as_ram.inc file.

The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.

Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S.  Drop the BIST check like other devices.

Move InitReset and InitEarly to bootblock.  These AGESA entry
points set some default settings, and release/recapture the
AP cores.  There are currently some early dependencies on
InitReset.  Future work should include:
 * Pull the necessary functionality from InitReset into bootblock
 * Move InitReset and InitEarly to car_stage_entry() and out of
   bootblock
   - Add a mechanism for the BSP to give the APs an address
     to call and skip most of bootblock and verstage (when
     available) (1)
   - Reunify BiosCallOuts.c and OemCustomize.c

(1) During the InitReset call, the BSP enables the APs by setting
    core enable bits in F18F0x1DC and APs begin fetching/executing
    from the reset vector.  The BSP waits for all APs to also
    reach InitReset, where they enter an endless loop.  The BSP
    sends a command to them to execute a HLT instruction and the
    BSP eventually returns from InitReset.  The goal would be to
    preserve this process but prevent APs from rerunning early
    code.

Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 38 insertions, 40 deletions

diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 8efe744384..473b118d11 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -1,7 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Intel Corporation..
+ * Copyright (C) 2017 Advanced Micro Devices
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,52 +15,49 @@
  */
 
 #include <stdint.h>
-#include <arch/io.h>
-#include <device/pci_ids.h>
-#include <soc/pci_devs.h>
+#include <console/console.h>
+#include <smp/node.h>
+#include <bootblock_common.h>
+#include <agesawrapper.h>
+#include <agesawrapper_call.h>
+#include <soc/hudson.h>
 
-/*
- * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
- *
- * Hardware should enable LPC ROM by pin straps. This function does not
- * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
- *
- * The HUDSON power-on default is to map 512K ROM space.
- *
- */
-static void hudson_enable_rom(void)
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
-	u8 reg8;
-	pci_devfn_t dev;
+	/*
+	 * Call lib/bootblock.c main with BSP, shortcut for APs
+	 *  todo: rearchitect AGESA entry points to remove need
+	 *        to run amdinitreset, amdinitearly from bootblock.
+	 *        Remove AP shortcut.
+	 */
+	if (!boot_cpu())
+		bootblock_soc_early_init(); /* APs will not return */
 
-	dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+	bootblock_main_with_timestamp(base_timestamp);
+}
 
-	/* Decode variable LPC ROM address ranges 1 and 2. */
-	reg8 = pci_io_read_config8(dev, 0x48);
-	reg8 |= (1 << 3) | (1 << 4);
-	pci_io_write_config8(dev, 0x48, reg8);
+void bootblock_soc_early_init(void)
+{
+	amd_initmmio();
 
-	/* LPC ROM address range 1: */
-	/* Enable LPC ROM range mirroring start at 0x000e(0000). */
-	pci_io_write_config16(dev, 0x68, 0x000e);
-	/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
-	pci_io_write_config16(dev, 0x6a, 0x000f);
+	if (!boot_cpu())
+		bootblock_soc_init(); /* APs will not return */
 
-	/* LPC ROM address range 2: */
-	/*
-	 * Enable LPC ROM range start at:
-	 * 0xfff8(0000): 512KB
-	 * 0xfff0(0000): 1MB
-	 * 0xffe0(0000): 2MB
-	 * 0xffc0(0000): 4MB
-	 */
-	pci_io_write_config16(dev, 0x6c, 0x10000
-					- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
-	/* Enable LPC ROM range end at 0xffff(ffff). */
-	pci_io_write_config16(dev, 0x6e, 0xffff);
+	bootblock_fch_early_init();
+
+	post_code(0x90);
+	if (CONFIG_STONEYRIDGE_UART)
+		configure_hudson_uart();
 }
 
-static void bootblock_southbridge_init(void)
+void bootblock_soc_init(void)
 {
-	hudson_enable_rom();
+	u32 val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
+
+	post_code(0x37);
+	AGESAWRAPPER(amdinitreset);
+
+	post_code(0x38);
+	AGESAWRAPPER(amdinitearly); /* APs will not exit amdinitearly */
 }