diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-06-15 12:17:38 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 20:50:54 +0000 |
| commit | 4e101ada37c10282030729f4a03fd505bd4f526d (patch) | |
| tree | 7cdb6f41b198ef1e9c30f66da854572893de91ed /src/soc/amd/stoneyridge/bootblock | |
| parent | 4692e2fc95605a997cd9cd1cdb711e6c1f6869bc (diff) | |
soc/amd/stoneyridge: Fix most checkpatch errors
Correct the majority of reported errors and mark most of the
remaining ones as todo. (Some of the lines requiring a >80
break are indented too much currently.) Some of the alignment
in hudson.h still causes checkpatch errors, but this is
intentionally left as-is.
Also make other misc. changes, e.g. consistency in lower-case
for hex values, using defined values, etc.
These changes were confirmed to cause no changes in a Gardenia
build. No other improvements were made, e.g. changing to helper
functions, or converting functions like __outbyte().
BUG=chrome-os-partner:622407746
Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/bootblock')
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock/bootblock.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 32b129862d..8efe744384 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <soc/pci_devs.h> /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -31,7 +32,7 @@ static void hudson_enable_rom(void) u8 reg8; pci_devfn_t dev; - dev = PCI_DEV(0, 0x14, 3); + dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_io_read_config8(dev, 0x48); @@ -52,7 +53,8 @@ static void hudson_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + pci_io_write_config16(dev, 0x6c, 0x10000 + - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ pci_io_write_config16(dev, 0x6e, 0xffff); } |