diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-08-04 19:21:47 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-08-11 17:38:36 +0000 |
| commit | e0b0697fedf756a811d0326426ab36a59dd83161 (patch) | |
| tree | 96198304184b90b3f401f874314eea8fa0141c2b /src/soc/amd/stoneyridge/acpi | |
| parent | 6f426784606735beeeaabd2ce6d4d6236912c5fe (diff) | |
soc/amd/stoneyridge/acpi: clean up global NVS
Some fields in GNVS seem to be copied over from Apollolake to
Stoneyridge. This patch removes the unused fields.
Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/globalnvs.asl | 38 |
1 files changed, 14 insertions, 24 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 2865352506..0acc408f0f 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -14,25 +14,15 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Miscellaneous */ Offset (0x00), PCNT, 8, // 0x00 - Processor Count - PPCM, 8, // 0x01 - Max PPC State - LIDS, 8, // 0x02 - LID State - PWRS, 8, // 0x03 - AC Power State - DPTE, 8, // 0x04 - Enable DPTF - CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console - PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index - GPEI, 64, // 0x11 - 0x18 - GPE Wake Source - NHLA, 64, // 0x19 - 0x20 - NHLT Address - NHLL, 32, // 0x21 - 0x24 - NHLT Length - PRT0, 32, // 0x25 - 0x28 - PERST_0 Address - SCDP, 8, // 0x29 - SD_CD GPIO portid - SCDO, 8, // 0x2A - GPIO pad offset relative to the community - TMPS, 8, // 0x2B - Temperature Sensor ID - TLVL, 8, // 0x2C - Throttle Level Limit - FLVL, 8, // 0x2D - Current FAN Level - TCRT, 8, // 0x2E - Critical Threshold - TPSV, 8, // 0x2F - Passive Threshold - TMAX, 8, // 0x30 - CPU Tj_max - Offset (0x34), // 0x34 - AOAC Device Enables + LIDS, 8, // 0x01 - LID State + PWRS, 8, // 0x02 - AC Power State + CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console + PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index + GPEI, 64, // 0x0f - 0x16 - GPE Wake Source + TMPS, 8, // 0x17 - Temperature Sensor ID + TCRT, 8, // 0x18 - Critical Threshold + TPSV, 8, // 0x19 - Passive Threshold + Offset (0x20), // 0x20 - AOAC Device Enables , 5, IC0E, 1, // I2C0, 5 IC1E, 1, // I2C1, 6 @@ -51,11 +41,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve) , 2, ESPI, 1, // ESPI, 27 , 4, - FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM - FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM - FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM - FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM - EH10, 32, // 0x44 - EHCI BAR + FW00, 16, // 0x24 - xHCI FW ROM addr, boot RAM + FW02, 16, // 0x26 - xHCI FW ROM addr, Instruction RAM + FW01, 32, // 0x28 - xHCI FW RAM addr, boot RAM + FW03, 32, // 0x2c - xHCI FW RAM addr, Instruction RAM + EH10, 32, // 0x30 - EHCI BAR /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> |