soc: Add AMD Stoney Ridge southbridge code

Copy the Hudson/Kern code from southbridge/amd/pi/hudson.  This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/

Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops

Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

7 files changed, 958 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/acpi/fch.asl b/src/soc/amd/stoneyridge/acpi/fch.asl
new file mode 100644
index 0000000000..df9caacf56
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/fch.asl
@@ -0,0 +1,184 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* South Bridge */
+/*  _SB.PCI0 */
+
+/* Operating System Capabilities Method */
+Method(_OSC,4)
+{
+	// Create DWord-addressable fields from the Capabilities Buffer
+	CreateDWordField(Arg3,0,CDW1)
+	CreateDWordField(Arg3,4,CDW2)
+	CreateDWordField(Arg3,8,CDW3)
+
+	/* Check for proper PCI/PCIe UUID */
+	If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+	{
+		/* Let OS control everything */
+		Return (Arg3)
+	} Else {
+		Or(CDW1,4,CDW1)	// Unrecognized UUID
+		Return(Arg3)
+	}
+}
+
+/* Describe the Southbridge devices */
+
+/* 0:11.0 - SATA */
+Device(STCR) {
+	Name(_ADR, 0x00110000)
+} /* end STCR */
+
+/* 0:14.0 - SMBUS */
+Device(SBUS) {
+	Name(_ADR, 0x00140000)
+} /* end SBUS */
+
+#include "usb.asl"
+
+/* 0:14.2 - I2S Audio */
+
+/* 0:14.3 - LPC */
+#include "lpc.asl"
+
+/* 0:14.7 - SD Controller */
+Device(SDCN) {
+	Name(_ADR, 0x00140007)
+} /* end SDCN */
+
+Name(CRES, ResourceTemplate() {
+	/* Set the Bus number and Secondary Bus number for the PCI0 device
+	 * The Secondary bus range for PCI0 lets the system
+	 * know what bus values are allowed on the downstream
+	 * side of this PCI bus if there is a PCI-PCI bridge.
+	 * PCI busses can have 256 secondary busses which
+	 * range from [0-0xFF] but they do not need to be
+	 * sequential.
+	 */
+	WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+		0x0000,		/* address granularity */
+		0x0000,		/* range minimum */
+		0x00FF,		/* range maximum */
+		0x0000,		/* translation */
+		0x0100,		/* length */
+		,, PSB0)		/* ResourceSourceIndex, ResourceSource, DescriptorName */
+
+	IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		0x0000,		/* address granularity */
+		0x0000,		/* range minimum */
+		0x0CF7,		/* range maximum */
+		0x0000,		/* translation */
+		0x0CF8		/* length */
+	)
+	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		0x0000,		/* address granularity */
+		0x03B0,		/* range minimum */
+		0x03DF,		/* range maximum */
+		0x0000,		/* translation */
+		0x0030		/* length */
+	)
+
+	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		0x0000,		/* address granularity */
+		0x0D00,		/* range minimum */
+		0xFFFF,		/* range maximum */
+		0x0000,		/* translation */
+		0xF300		/* length */
+	)
+
+	Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
+	Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+
+	/* memory space for PCI BARs below 4GB */
+	Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+}) /* End Name(_SB.PCI0.CRES) */
+
+Method(_CRS, 0) {
+	/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+	CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+	CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+
+	/*
+	 * Declare memory between TOM1 and 4GB as available
+	 * for PCI MMIO.
+	 * Use ShiftLeft to avoid 64bit constant (for XP).
+	 * This will work even if the OS does 32bit arithmetic, as
+	 * 32bit (0x00000000 - TOM1) will wrap and give the same
+	 * result as 64bit (0x100000000 - TOM1).
+	 */
+	Store(TOM1, MM1B)
+	ShiftLeft(0x10000000, 4, Local0)
+	Subtract(Local0, TOM1, Local0)
+	Store(Local0, MM1L)
+
+	Return(CRES) /* note to change the Name buffer */
+} /* end of Method(_SB.PCI0._CRS) */
+
+/*
+ *
+ *               FIRST METHOD CALLED UPON BOOT
+ *
+ *  1. If debugging, print current OS and ACPI interpreter.
+ *  2. Get PCI Interrupt routing from ACPI VSM, this
+ *     value is based on user choice in BIOS setup.
+ */
+Method(_INI, 0) {
+	/* DBGO("\\_SB\\_INI\n") */
+	/* DBGO("   DSDT.ASL code from ") */
+	/* DBGO(__DATE__) */
+	/* DBGO(" ") */
+	/* DBGO(__TIME__) */
+	/* DBGO("\n   Sleep states supported: ") */
+	/* DBGO("\n") */
+	/* DBGO("   \\_OS=") */
+	/* DBGO(\_OS) */
+	/* DBGO("\n   \\_REV=") */
+	/* DBGO(\_REV) */
+	/* DBGO("\n") */
+
+	/* Determine the OS we're running on */
+	OSFL()
+
+#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)
+	/* TODO: It is unstable. */
+	#include "acpi/AmdImc.asl" /* Hudson IMC function */
+	ITZE() /* enable IMC Fan Control*/
+#endif
+} /* End Method(_SB._INI) */
+
+Method(OSFL, 0){
+
+	if (LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
+
+	if (CondRefOf(\_OSI))
+	{
+		Store(1, OSVR)					/* Assume some form of XP */
+		if (\_OSI("Windows 2006"))		/* Vista */
+		{
+			Store(2, OSVR)
+		}
+	} else {
+		If(WCMP(\_OS,"Linux")) {
+			Store(3, OSVR)				/* Linux */
+		} Else {
+			Store(4, OSVR)				/* Gotta be WinCE */
+		}
+	}
+	Return(OSVR)
+}
diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/stoneyridge/acpi/lpc.asl
new file mode 100644
index 0000000000..6332d47152
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/lpc.asl
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* 0:14.3 - LPC */
+Device(LIBR) {
+	Name(_ADR, 0x00140003)
+	/* Method(_INI) {
+	*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+	} */ /* End Method(_SB.SBRDG._INI) */
+
+	OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
+	Field(CFG,DWordAcc,NoLock,Preserve){
+		Offset(0xA0),
+		BAR,32}		// SPI Controller Base Address Register (Index 0xA0)
+
+	Device(LDRC)	// LPC device: Resource consumption
+	{
+		Name (_HID, EISAID("PNP0C02"))  // ID for Motherboard resources
+		Name (CRS, ResourceTemplate ()  // Current Motherboard resources
+		{
+			Memory32Fixed(ReadWrite,	// Setup for fixed resource location for SPI base address
+			0x00000000,			// Address Base
+			0x00000000,			// Address Length
+			BAR0				// Descriptor Name
+			)
+		})
+
+		Method(_CRS,0,NotSerialized)
+		{
+			CreateDwordField(^CRS,^BAR0._BAS,SPIB)	// Field to hold SPI base address
+			CreateDwordField(^CRS,^BAR0._LEN,SPIL)	// Field to hold SPI address length
+			Store(BAR,SPIB)		// SPI base address mapped
+			Store(0x1000,SPIL)	// 4k space mapped
+			Return(CRS)
+		}
+	}
+
+	/* Real Time Clock Device */
+	Device(RTC0) {
+		Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
+		Name(_CRS, ResourceTemplate() {
+			IRQNoFlags(){8}
+			IO(Decode16,0x0070, 0x0070, 0, 2)
+		})
+	} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+	Device(TMR) {	/* Timer */
+		Name(_HID,EISAID("PNP0100"))	/* System Timer */
+		Name(_CRS, ResourceTemplate() {
+			IRQNoFlags(){0}
+			IO(Decode16, 0x0040, 0x0040, 0, 4)
+		})
+	} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+	Device(SPKR) {	/* Speaker */
+		Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+		Name(_CRS, ResourceTemplate() {
+			IO(Decode16, 0x0061, 0x0061, 0, 1)
+		})
+	} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+	Device(PIC) {
+		Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+		Name(_CRS, ResourceTemplate() {
+			IRQNoFlags(){2}
+			IO(Decode16,0x0020, 0x0020, 0, 2)
+			IO(Decode16,0x00A0, 0x00A0, 0, 2)
+		})
+	} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+	Device(MAD) { /* 8257 DMA */
+		Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+		Name(_CRS, ResourceTemplate() {
+			DMA(Compatibility,BusMaster,Transfer8){4}
+			IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+			IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+			IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+			IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+			IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+			IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+		}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+	} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+	Device(COPR) {
+		Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+		Name(_CRS, ResourceTemplate() {
+			IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+			IRQNoFlags(){13}
+		})
+	} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+} /* end LIBR */
diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl
new file mode 100644
index 0000000000..52e9e28e39
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl
@@ -0,0 +1,469 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+	/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
+	OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
+		Field(PCFG, ByteAcc, NoLock, Preserve) {
+		/* Byte offsets are computed using the following technique:
+		 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+		 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+		*/
+		Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+		STB5, 32,
+		Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+		PT0D, 1,
+		PT1D, 1,
+		PT2D, 1,
+		PT3D, 1,
+		PT4D, 1,
+		PT5D, 1,
+		PT6D, 1,
+		PT7D, 1,
+		PT8D, 1,
+		PT9D, 1,
+		Offset(0x000A0004),	/* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+		SBIE, 1,
+		SBME, 1,
+		Offset(0x000A0008),	/* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+		SBRI, 8,
+		Offset(0x000A0014),	/* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+		SBB1, 32,
+		Offset(0x000A0078),	/* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+		,14,
+		P92E, 1,		/* Port92 decode enable */
+	}
+
+	OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+		Field(SB5, AnyAcc, NoLock, Preserve){
+		/* Port 0 */
+		Offset(0x120),		/* Port 0 Task file status */
+		P0ER, 1,
+		, 2,
+		P0DQ, 1,
+		, 3,
+		P0BY, 1,
+		Offset(0x128),		/* Port 0 Serial ATA status */
+		P0DD, 4,
+		, 4,
+		P0IS, 4,
+		Offset(0x12C),		/* Port 0 Serial ATA control */
+		P0DI, 4,
+		Offset(0x130),		/* Port 0 Serial ATA error */
+		, 16,
+		P0PR, 1,
+
+		/* Port 1 */
+		offset(0x1A0),		/* Port 1 Task file status */
+		P1ER, 1,
+		, 2,
+		P1DQ, 1,
+		, 3,
+		P1BY, 1,
+		Offset(0x1A8),		/* Port 1 Serial ATA status */
+		P1DD, 4,
+		, 4,
+		P1IS, 4,
+		Offset(0x1AC),		/* Port 1 Serial ATA control */
+		P1DI, 4,
+		Offset(0x1B0),		/* Port 1 Serial ATA error */
+		, 16,
+		P1PR, 1,
+
+		/* Port 2 */
+		Offset(0x220),		/* Port 2 Task file status */
+		P2ER, 1,
+		, 2,
+		P2DQ, 1,
+		, 3,
+		P2BY, 1,
+		Offset(0x228),		/* Port 2 Serial ATA status */
+		P2DD, 4,
+		, 4,
+		P2IS, 4,
+		Offset(0x22C),		/* Port 2 Serial ATA control */
+		P2DI, 4,
+		Offset(0x230),		/* Port 2 Serial ATA error */
+		, 16,
+		P2PR, 1,
+
+		/* Port 3 */
+		Offset(0x2A0),		/* Port 3 Task file status */
+		P3ER, 1,
+		, 2,
+		P3DQ, 1,
+		, 3,
+		P3BY, 1,
+		Offset(0x2A8),		/* Port 3 Serial ATA status */
+		P3DD, 4,
+		, 4,
+		P3IS, 4,
+		Offset(0x2AC),		/* Port 3 Serial ATA control */
+		P3DI, 4,
+		Offset(0x2B0),		/* Port 3 Serial ATA error */
+		, 16,
+		P3PR, 1,
+	}
+
+	Method(_PIC, 0x01, NotSerialized)
+	{
+		If (Arg0)
+		{
+			\_SB.CIRQ()
+		}
+		Store(Arg0, PMOD)
+	}
+
+	Method(CIRQ, 0x00, NotSerialized){
+	}
+
+	Name(IRQB, ResourceTemplate(){
+		IRQ(Level,ActiveLow,Shared){15}
+	})
+
+	Name(IRQP, ResourceTemplate(){
+		IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+	})
+
+	Name(PITF, ResourceTemplate(){
+		IRQ(Level,ActiveLow,Exclusive){9}
+	})
+
+	Device(INTA) {
+		Name(_HID, EISAID("PNP0C0F"))
+		Name(_UID, 1)
+
+		Method(_STA, 0) {
+			if (PIRA) {
+				Return(0x0B) /* sata is invisible */
+			} else {
+				Return(0x09) /* sata is disabled */
+			}
+		} /* End Method(_SB.INTA._STA) */
+
+		Method(_DIS ,0) {
+			/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+		} /* End Method(_SB.INTA._DIS) */
+
+		Method(_PRS ,0) {
+			/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+			Return(IRQP)
+		} /* Method(_SB.INTA._PRS) */
+
+		Method(_CRS ,0) {
+			/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+			CreateWordField(IRQB, 0x1, IRQN)
+			ShiftLeft(1, PIRA, IRQN)
+			Return(IRQB)
+		} /* Method(_SB.INTA._CRS) */
+
+		Method(_SRS, 1) {
+			/* DBGO("\\_SB\\LNKA\\_SRS\n") */
+			CreateWordField(ARG0, 1, IRQM)
+
+			/* Use lowest available IRQ */
+			FindSetRightBit(IRQM, Local0)
+			if (Local0) {
+				Decrement(Local0)
+			}
+			Store(Local0, PIRA)
+		} /* End Method(_SB.INTA._SRS) */
+	} /* End Device(INTA) */
+
+	Device(INTB) {
+		Name(_HID, EISAID("PNP0C0F"))
+		Name(_UID, 2)
+
+		Method(_STA, 0) {
+			if (PIRB) {
+				Return(0x0B) /* sata is invisible */
+			} else {
+				Return(0x09) /* sata is disabled */
+			}
+		} /* End Method(_SB.INTB._STA) */
+
+		Method(_DIS ,0) {
+			/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+		} /* End Method(_SB.INTB._DIS) */
+
+		Method(_PRS ,0) {
+			/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+			Return(IRQP)
+		} /* Method(_SB.INTB._PRS) */
+
+		Method(_CRS ,0) {
+			/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+			CreateWordField(IRQB, 0x1, IRQN)
+			ShiftLeft(1, PIRB, IRQN)
+			Return(IRQB)
+		} /* Method(_SB.INTB._CRS) */
+
+		Method(_SRS, 1) {
+			/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+			CreateWordField(ARG0, 1, IRQM)
+
+			/* Use lowest available IRQ */
+			FindSetRightBit(IRQM, Local0)
+			if (Local0) {
+				Decrement(Local0)
+			}
+			Store(Local0, PIRB)
+		} /* End Method(_SB.INTB._SRS) */
+	} /* End Device(INTB)  */
+
+	Device(INTC) {
+		Name(_HID, EISAID("PNP0C0F"))
+		Name(_UID, 3)
+
+		Method(_STA, 0) {
+			if (PIRC) {
+				Return(0x0B) /* sata is invisible */
+			} else {
+				Return(0x09) /* sata is disabled */
+			}
+		} /* End Method(_SB.INTC._STA) */
+
+		Method(_DIS ,0) {
+			/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+		} /* End Method(_SB.INTC._DIS) */
+
+		Method(_PRS ,0) {
+			/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+			Return(IRQP)
+		} /* Method(_SB.INTC._PRS) */
+
+		Method(_CRS ,0) {
+			/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+			CreateWordField(IRQB, 0x1, IRQN)
+			ShiftLeft(1, PIRC, IRQN)
+			Return(IRQB)
+		} /* Method(_SB.INTC._CRS) */
+
+		Method(_SRS, 1) {
+			/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+			CreateWordField(ARG0, 1, IRQM)
+
+			/* Use lowest available IRQ */
+			FindSetRightBit(IRQM, Local0)
+			if (Local0) {
+				Decrement(Local0)
+			}
+			Store(Local0, PIRC)
+		} /* End Method(_SB.INTC._SRS) */
+	} /* End Device(INTC)  */
+
+	Device(INTD) {
+		Name(_HID, EISAID("PNP0C0F"))
+		Name(_UID, 4)
+
+		Method(_STA, 0) {
+			if (PIRD) {
+				Return(0x0B) /* sata is invisible */
+			} else {
+				Return(0x09) /* sata is disabled */
+			}
+		} /* End Method(_SB.INTD._STA) */
+
+		Method(_DIS ,0) {
+			/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+		} /* End Method(_SB.INTD._DIS) */
+
+		Method(_PRS ,0) {
+			/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+			Return(IRQP)
+		} /* Method(_SB.INTD._PRS) */
+
+		Method(_CRS ,0) {
+			/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+			CreateWordField(IRQB, 0x1, IRQN)
+			ShiftLeft(1, PIRD, IRQN)
+			Return(IRQB)
+		} /* Method(_SB.INTD._CRS) */
+
+		Method(_SRS, 1) {
+			/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+			CreateWordField(ARG0, 1, IRQM)
+
+			/* Use lowest available IRQ */
+			FindSetRightBit(IRQM, Local0)
+			if (Local0) {
+				Decrement(Local0)
+			}
+			Store(Local0, PIRD)
+		} /* End Method(_SB.INTD._SRS) */
+	} /* End Device(INTD)  */
+
+	Device(INTE) {
+		Name(_HID, EISAID("PNP0C0F"))
+		Name(_UID, 5)
+
+		Method(_STA, 0) {
+			if (PIRE) {
+				Return(0x0B) /* sata is invisible */
+			} else {
+				Return(0x09) /* sata is disabled */
+			}
+		} /* End Method(_SB.INTE._STA) */
+
+		Method(_DIS ,0) {
+			/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+		} /* End Method(_SB.INTE._DIS) */
+
+		Method(_PRS ,0) {
+			/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+			Return(IRQP)
+		} /* Method(_SB.INTE._PRS) */
+
+		Method(_CRS ,0) {
+			/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+			CreateWordField(IRQB, 0x1, IRQN)
+			ShiftLeft(1, PIRE, IRQN)
+			Return(IRQB)
+		} /* Method(_SB.INTE._CRS) */
+
+		Method(_SRS, 1) {
+			/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+			CreateWordField(ARG0, 1, IRQM)
+
+			/* Use lowest available IRQ */
+			FindSetRightBit(IRQM, Local0)
+			if (Local0) {
+				Decrement(Local0)
+			}
+			Store(Local0, PIRE)
+		} /* End Method(_SB.INTE._SRS) */
+	} /* End Device(INTE)  */
+
+	Device(INTF) {
+		Name(_HID, EISAID("PNP0C0F"))
+		Name(_UID, 6)
+
+		Method(_STA, 0) {
+			if (PIRF) {
+				Return(0x0B) /* sata is invisible */
+			} else {
+				Return(0x09) /* sata is disabled */
+			}
+		} /* End Method(_SB.INTF._STA) */
+
+		Method(_DIS ,0) {
+			/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+		} /* End Method(_SB.INTF._DIS) */
+
+		Method(_PRS ,0) {
+			/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+			Return(PITF)
+		} /* Method(_SB.INTF._PRS) */
+
+		Method(_CRS ,0) {
+			/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+			CreateWordField(IRQB, 0x1, IRQN)
+			ShiftLeft(1, PIRF, IRQN)
+			Return(IRQB)
+		} /* Method(_SB.INTF._CRS) */
+
+		Method(_SRS, 1) {
+			/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+			CreateWordField(ARG0, 1, IRQM)
+
+			/* Use lowest available IRQ */
+			FindSetRightBit(IRQM, Local0)
+			if (Local0) {
+				Decrement(Local0)
+			}
+			Store(Local0, PIRF)
+		} /*  End Method(_SB.INTF._SRS) */
+	} /* End Device(INTF)  */
+
+	Device(INTG) {
+		Name(_HID, EISAID("PNP0C0F"))
+		Name(_UID, 7)
+
+		Method(_STA, 0) {
+			if (PIRG) {
+				Return(0x0B) /* sata is invisible */
+			} else {
+				Return(0x09) /* sata is disabled */
+			}
+		} /* End Method(_SB.INTG._STA)  */
+
+		Method(_DIS ,0) {
+			/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+		} /* End Method(_SB.INTG._DIS)  */
+
+		Method(_PRS ,0) {
+			/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+			Return(IRQP)
+		} /* Method(_SB.INTG._CRS)  */
+
+		Method(_CRS ,0) {
+			/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+			CreateWordField(IRQB, 0x1, IRQN)
+			ShiftLeft(1, PIRG, IRQN)
+			Return(IRQB)
+		} /* Method(_SB.INTG._CRS)  */
+
+		Method(_SRS, 1) {
+			/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+			CreateWordField(ARG0, 1, IRQM)
+
+			/* Use lowest available IRQ */
+			FindSetRightBit(IRQM, Local0)
+			if (Local0) {
+				Decrement(Local0)
+			}
+			Store(Local0, PIRG)
+		} /* End Method(_SB.INTG._SRS)  */
+	} /* End Device(INTG)  */
+
+	Device(INTH) {
+		Name(_HID, EISAID("PNP0C0F"))
+		Name(_UID, 8)
+
+		Method(_STA, 0) {
+			if (PIRH) {
+				Return(0x0B) /* sata is invisible */
+			} else {
+				Return(0x09) /* sata is disabled */
+			}
+		} /* End Method(_SB.INTH._STA)  */
+
+		Method(_DIS ,0) {
+			/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+		} /* End Method(_SB.INTH._DIS)  */
+
+		Method(_PRS ,0) {
+			/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+			Return(IRQP)
+		} /* Method(_SB.INTH._CRS)  */
+
+		Method(_CRS ,0) {
+			/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+			CreateWordField(IRQB, 0x1, IRQN)
+			ShiftLeft(1, PIRH, IRQN)
+			Return(IRQB)
+		} /* Method(_SB.INTH._CRS)  */
+
+		Method(_SRS, 1) {
+			/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+			CreateWordField(ARG0, 1, IRQM)
+
+			/* Use lowest available IRQ */
+			FindSetRightBit(IRQM, Local0)
+			if (Local0) {
+				Decrement(Local0)
+			}
+			Store(Local0, PIRH)
+		} /* End Method(_SB.INTH._SRS)  */
+	} /* End Device(INTH)   */
diff --git a/src/soc/amd/stoneyridge/acpi/pcie.asl b/src/soc/amd/stoneyridge/acpi/pcie.asl
new file mode 100644
index 0000000000..adb5c4d2bf
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/pcie.asl
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+	/* PCI IRQ mapping registers, C00h-C01h. */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PIRA, 0x00000008,	/* Index 0 */
+		PIRB, 0x00000008,	/* Index 1 */
+		PIRC, 0x00000008,	/* Index 2 */
+		PIRD, 0x00000008,	/* Index 3 */
+		PIRE, 0x00000008,	/* Index 4 */
+		PIRF, 0x00000008,	/* Index 5 */
+		PIRG, 0x00000008,	/* Index 6 */
+		PIRH, 0x00000008,	/* Index 7 */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,	8,
+		/* Client Management Data register */
+		G64E,	1,
+		G64O,	1,
+		G32O,	2,
+		,		2,
+		GPSL,	2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x60),		/* AcpiPm1EvgBlk */
+		P1EB, 16,
+		Offset(0xEE),
+		UPWS, 3,
+	}
+	OperationRegion (P1E0, SystemIO, P1EB, 0x04)
+		Field (P1E0, ByteAcc, Nolock, Preserve) {
+		Offset(0x02),
+		, 14,
+		PEWD, 1,
+	}
diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl
new file mode 100644
index 0000000000..d93f068bb7
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Supported sleep states: */
+Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+If (LAnd(SSFG, 0x01)) {
+	Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+}
+If (LAnd(SSFG, 0x02)) {
+	Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+}
+#if CONFIG_HAVE_ACPI_RESUME
+If (LAnd(SSFG, 0x04)) {
+	Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+}
+#endif
+If (LAnd(SSFG, 0x08)) {
+	Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+}
+
+Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+Name(\_SB.CSPS ,0)	/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+Name(CSMS, 0)		/* Current System State */
diff --git a/src/soc/amd/stoneyridge/acpi/smbus.asl b/src/soc/amd/stoneyridge/acpi/smbus.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/smbus.asl
diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl
new file mode 100644
index 0000000000..fd3ff54f7d
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/usb.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* 0:12.0 - OHCI */
+Device(UOH1) {
+	Name(_ADR, 0x00120000)
+	Name(_PRW, Package() {0x0B, 3})
+} /* end UOH1 */
+
+/* 0:12.2 - EHCI */
+Device(UOH2) {
+	Name(_ADR, 0x00120002)
+	Name(_PRW, Package() {0x0B, 3})
+} /* end UOH2 */
+
+/* 0:13.0 - OHCI */
+Device(UOH3) {
+	Name(_ADR, 0x00130000)
+	Name(_PRW, Package() {0x0B, 3})
+} /* end UOH3 */
+
+/* 0:13.2 - EHCI */
+Device(UOH4) {
+	Name(_ADR, 0x00130002)
+	Name(_PRW, Package() {0x0B, 3})
+} /* end UOH4 */
+
+/* 0:16.0 - OHCI */
+Device(UOH5) {
+	Name(_ADR, 0x00160000)
+	Name(_PRW, Package() {0x0B, 3})
+} /* end UOH5 */
+
+/* 0:16.2 - EHCI */
+Device(UOH6) {
+	Name(_ADR, 0x00160002)
+	Name(_PRW, Package() {0x0B, 3})
+} /* end UOH5 */
+
+/* 0:10.0 - XHCI 0*/
+Device(XHC0) {
+	Name(_ADR, 0x00100000)
+	Name(_PRW, Package() {0x0B, 4})
+} /* end XHC0 */
+
+#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN
+/* 0:10.1 - XHCI 1*/
+Device(XHC1) {
+	Name(_ADR, 0x00100001)
+	Name(_PRW, Package() {0x0B, 4})
+} /* end XHC1 */
+#endif