diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2019-06-28 09:18:47 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-31 09:11:05 +0000 |
| commit | 9247e86f288fadf2fcff4b61a64f05cbf6e60b1e (patch) | |
| tree | cb433b52ead9ca8c50a6d62f3c796702ccb62be3 /src/soc/amd/stoneyridge/acpi | |
| parent | cac5e9472622f43c0b33d70f20adef801b345773 (diff) | |
soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOC
Stoney Ridge is family 15h models 70h-7Fh, Merlin Falcon is family 15h models
60h-6Fh. Add changes based on config parameter SOC_AMD_MERLINFALCON to make
the code backward compatible with Merlin Falcon.
BUG=none.
TEST=Tested later with padmelon board.
Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33624
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/cpu.asl | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 414326ecf1..94638b043d 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -34,7 +34,15 @@ External (\_PR.P007, DeviceObj) /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 2)) { + If (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + \_PR.P000, + \_PR.P001, + \_PR.P002, + \_PR.P003 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { \_PR.P000, |