diff options
author | Marc Jones <marcj303@gmail.com> | 2017-05-04 21:17:45 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:45:41 +0000 |
commit | 244848462def7075e0c812a2f71c408668cacfe4 (patch) | |
tree | fde926f45d478b36eaebfd1261886c973b803857 /src/soc/amd/stoneyridge/acpi/usb.asl | |
parent | a0199d8e1a96d94828b31f77e0a29a282871a76a (diff) |
soc: Add AMD Stoney Ridge southbridge code
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/
Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops
Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi/usb.asl')
-rw-r--r-- | src/soc/amd/stoneyridge/acpi/usb.asl | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl new file mode 100644 index 0000000000..fd3ff54f7d --- /dev/null +++ b/src/soc/amd/stoneyridge/acpi/usb.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* 0:12.0 - OHCI */ +Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH1 */ + +/* 0:12.2 - EHCI */ +Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH2 */ + +/* 0:13.0 - OHCI */ +Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH3 */ + +/* 0:13.2 - EHCI */ +Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH4 */ + +/* 0:16.0 - OHCI */ +Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH5 */ + +/* 0:16.2 - EHCI */ +Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH5 */ + +/* 0:10.0 - XHCI 0*/ +Device(XHC0) { + Name(_ADR, 0x00100000) + Name(_PRW, Package() {0x0B, 4}) +} /* end XHC0 */ + +#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN +/* 0:10.1 - XHCI 1*/ +Device(XHC1) { + Name(_ADR, 0x00100001) + Name(_PRW, Package() {0x0B, 4}) +} /* end XHC1 */ +#endif |