diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-09-26 15:43:21 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-01 15:03:49 +0000 |
| commit | fdb846ddf270e5a3406a835fb67a5c1b049f9bf3 (patch) | |
| tree | 4a30964f3f00bdb1fc0264ac607fb3773037e094 /src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | |
| parent | cb2b70b3d205d4352bf92e917b8f7c1e9a12a032 (diff) | |
amd/stoneyridge: Add USB ASL for D0/D3cold
Add methods, and call them, for transitioning EHCI and xHCI to D0 or
D3cold. Add device objects necessary for waking the system via USB.
In order for USB to wake the system, it must be in the D3cold state.
Then on resume, its firmware must be reloaded.
This code relies heavily on AMD's FchCarrizo.asl (delivered in NDA PI
package), and has been modified to fit the coreboot ASL names. In
addition, AMD's methodology is to generate a SW SMI for saving/restoring
certain settings. This has been ported into U3D0 and U3D3, as the
necessary registers are now publicly documented.
BUG=b:77602074
Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28772
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index e875f43f40..77c288b870 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -499,8 +499,8 @@ Method(FDDC, 2, Serialized) } } /* todo Case(15) { STD0()} */ /* SATA */ -/* todo Case(18) { U2D0()} */ /* EHCI */ -/* todo Case(23) { U3D0()} */ /* XHCI */ + Case(18) { U2D0()} /* EHCI */ + Case(23) { U3D0()} /* XHCI */ /* todo Case(24) { SDD0()} */ /* SD */ } } else { @@ -555,8 +555,8 @@ Method(FDDC, 2, Serialized) Store(0x03, U1TD) } /* todo Case(15) { STD3()} */ /* SATA */ -/* todo Case(18) { U2D3()} */ /* EHCI */ -/* todo Case(23) { U3D3()} */ /* XHCI */ + Case(18) { U2D3()} /* EHCI */ + Case(23) { U3D3()} /* XHCI */ /* todo Case(24) { SDD3()} */ /* SD */ } /* Turn off Power */ |