diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-29 09:24:18 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-06-06 18:50:28 +0000 |
| commit | 6ab5ed3b66fc215d0d03b19ab02fdcf8613c7d09 (patch) | |
| tree | 0a1512a069659f4f16412cb21f5357daa047aa38 /src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | |
| parent | eceaa97b27b04a61dd5fb2e68e0f5ac1367a3c0f (diff) | |
soc/amd/stoneyridge: Move LPC support to common
AMD devices traditionally have the LPC-ISA bus at 14.3 and the
definition has been very consistent. Relocate the feature from
stoneyridge into common/block.
BUG=b:131682806
Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 1334df11c4..3623814080 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -51,7 +51,7 @@ Device(SBUS) { /* 0:14.2 - I2S Audio */ /* 0:14.3 - LPC */ -#include "lpc.asl" +#include <soc/amd/common/acpi/lpc.asl> /* 0:14.7 - SD Controller */ Device(SDCN) { |