diff options
| author | Chris Ching <chingcodes@google.com> | 2017-10-19 11:45:30 -0600 |
|---|---|---|
| committer | Chris Ching <chingcodes@chromium.org> | 2017-10-19 21:07:10 +0000 |
| commit | 6a35fab2723f3b1ca288cd9224d263570cfbe184 (patch) | |
| tree | 5b07742b8fe915db4d1fddc1af320a670f7ba699 /src/soc/amd/stoneyridge/acpi.c | |
| parent | c5ecd3e14d17c5634247242afc8cd558c1ae158f (diff) | |
soc/amd/stoneyridge: Use macros for PCI_DEVFN calls
* Change all calls to PCI_DEVFN to macros
* Remove CBB and CDB Kconfig since these are static for stoneyridge
BUG=b:62200746
TEST=build
Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index e6e785c1a8..02ee6fa02f 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -29,6 +29,7 @@ #include <device/device.h> #include <device/pci.h> #include <soc/acpi.h> +#include <soc/pci_devs.h> #include <soc/southbridge.h> #include <soc/nvs.h> @@ -239,7 +240,7 @@ void generate_cpu_entries(device_t device) device_t cdb_dev; /* Stoney Ridge is single node, just report # of cores */ - cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5)); + cdb_dev = dev_find_slot(0, NB_DEVFN); cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1; printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); |