diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-14 10:20:03 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-21 09:38:26 +0000 |
| commit | 67c48a36776695b956ea49eb308c1025e430b475 (patch) | |
| tree | 47dbf975b060fec1656166fbbc08a97122c8ed72 /src/soc/amd/stoneyridge/acpi.c | |
| parent | 88fefd4feb61d20945a1be4a792f8236db1bb2d0 (diff) | |
ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
After the obsoletion of Processor() it is necessary to provide
_CST package to define P_LVLx IO addresses for C2/C3 transitions.
The latency values from _CST will always replace those in FADT.
Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 947c806197..d6dec6f54d 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -71,10 +71,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fill_fadt_extended_pm_regs(fadt); - /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the PSTATE SSDT. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = RTC_DATE_ALARM; |