diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-15 05:58:42 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-16 09:28:42 +0000 |
| commit | 4de1a31cb04f0363b6d257d9de392cdfe8d5644c (patch) | |
| tree | 80a674e5d82d33c5e133d31676ab48bad409798e /src/soc/amd/stoneyridge/acpi.c | |
| parent | cdd2f63947549e9b478f26942daf400cf4f246e6 (diff) | |
ACPI: Add acpi_reset_gnvs_for_wake()
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 8007e6789f..8b97ace47e 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -7,7 +7,6 @@ #include <string.h> #include <console/console.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <device/pci_ops.h> #include <arch/ioapic.h> @@ -21,7 +20,6 @@ #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <soc/northbridge.h> -#include <soc/nvs.h> #include <soc/gpio.h> #include <version.h> @@ -159,13 +157,6 @@ void generate_cpu_entries(const struct device *device) acpigen_pop_len(); } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - /* Set unknown wake source */ - gnvs->pm1i = ~0ULL; - gnvs->gpei = ~0ULL; -} - static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) { /* |