soc/amd/common: Drop ACPIMMIO GPIO bank separation

The banks are one after each other in the ACPIMMIO space. Also
there is space for more banks and existing ASL takes advantage
of the property.

Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42522
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index ffead50435..19dee79a96 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -277,7 +277,7 @@ static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
 					" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
 		return -1;
 	}
-	uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
+	uintptr_t addr = gpio_get_address(gpio_num);
 
 	acpigen_soc_get_gpio_in_local5(addr);
 
@@ -307,7 +307,7 @@ static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
 					" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
 		return -1;
 	}
-	uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
+	uintptr_t addr = gpio_get_address(gpio_num);
 
 	/* Store (0x40, Local0) */
 	acpigen_write_store();