diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-12 23:44:05 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-14 15:00:55 +0000 |
| commit | 91ef92525d8a9a0e83be8d91eb5e83b1cab58008 (patch) | |
| tree | 15f519bee3a44bbb2a462a3667ea31a30259d274 /src/soc/amd/stoneyridge/Makefile.inc | |
| parent | 6f9ed7a10dfb8763a13f09d65c7faa36b3bacd64 (diff) | |
soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UART
Since the functions that get called by the coreboot console
initialization code aren't in the SOC-specific code anymore, the SOC's
uart.c can be included unconditionally in the build now. This also
replaces the STONEYRIDGE_UART Kconfig option with the common
AMD_SOC_CONSOLE_UART one.
Change-Id: I09c15566a402895d6388715e8e5a802dc3c94fdd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/Makefile.inc')
| -rw-r--r-- | src/soc/amd/stoneyridge/Makefile.inc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 2ad07306b3..6f9a3051a1 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -10,7 +10,7 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm -bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c +bootblock-y += uart.c bootblock-y += BiosCallOuts.c bootblock-y += bootblock.c bootblock-y += gpio.c @@ -28,7 +28,7 @@ romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += smbus_spd.c romstage-y += memmap.c -romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +romstage-y += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-y += psp.c @@ -36,11 +36,11 @@ romstage-y += psp.c verstage-y += gpio.c verstage-y += i2c.c verstage-y += monotonic_timer.c -verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +verstage-y += uart.c verstage-y += tsc_freq.c postcar-y += monotonic_timer.c -postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c +postcar-y += uart.c postcar-y += memmap.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -59,7 +59,7 @@ ramstage-y += northbridge.c ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +ramstage-y += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c |