diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-02 22:55:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-04 14:02:27 +0000 |
| commit | 3bdbdb77a2ab8904487266b26a33b18c7d85e28b (patch) | |
| tree | 95074dfebbd676215f0894bd2466cec11a1c0ded /src/soc/amd/sabrina | |
| parent | 6d1db72958cf8b4fc351c983f5dd1f5068a49974 (diff) | |
soc/amd/common/block/i2c/i23c_pad_ctr: add & use I23C pad configuration
I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V
and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the
existing I2C pad control registers the bit definitions are different, so
add a separate function to configure those pads which however still has
the same function signature and is compatible with same data structs
used for the devicetree settings. PPR #57243 Rev 1.50 was used as a
reference.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/sabrina')
| -rw-r--r-- | src/soc/amd/sabrina/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/i2c.c | 7 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 2e34e3f519..c24f1a3a47 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -53,6 +53,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct diff --git a/src/soc/amd/sabrina/i2c.c b/src/soc/amd/sabrina/i2c.c index 88da74e224..d9a9e44506 100644 --- a/src/soc/amd/sabrina/i2c.c +++ b/src/soc/amd/sabrina/i2c.c @@ -41,7 +41,12 @@ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) if (bus >= ARRAY_SIZE(config->i2c_pad)) return; - fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); + /* The I/O pads of I2C0..2 are the new I23C pads and the I/O pads of I2C3 still are the + same I2C pads as in Picasso and Cezanne. */ + if (bus <= 2) + fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); + else + fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) |