summaryrefslogtreecommitdiff
path: root/src/soc/amd/sabrina
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2021-05-29 07:30:33 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-06-07 12:54:39 +0000
commitbab9e2e6bdf3bbfa6047773a04632e0fbdf64afb (patch)
treeab42496f77d4bf76f3f9f79eea16ddc92d8a5cd6 /src/soc/amd/sabrina
parent11cac784ff788b4f0495758d7f5992e457ea552c (diff)
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that will be for a later commit. Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/soc/amd/sabrina')
-rw-r--r--src/soc/amd/sabrina/romstage.c11
1 files changed, 3 insertions, 8 deletions
diff --git a/src/soc/amd/sabrina/romstage.c b/src/soc/amd/sabrina/romstage.c
index 49ca223c60..c5dfbdaa18 100644
--- a/src/soc/amd/sabrina/romstage.c
+++ b/src/soc/amd/sabrina/romstage.c
@@ -10,18 +10,12 @@
#include <console/console.h>
#include <fsp/api.h>
#include <program_loading.h>
-#include <timestamp.h>
+#include <romstage_common.h>
-asmlinkage void car_stage_entry(void)
+void __noreturn romstage_main(void)
{
- timestamp_add_now(TS_ROMSTAGE_START);
-
post_code(0x40);
- console_init();
-
- post_code(0x41);
-
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
@@ -33,4 +27,5 @@ asmlinkage void car_stage_entry(void)
memmap_stash_early_dram_usage();
run_ramstage();
+ die("failed to load ramstage\n");
}