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authorJon Murphy <jpmurphy@google.com>2022-02-24 14:37:04 -0700
committerFelix Held <felix-coreboot@felixheld.de>2022-02-28 13:29:24 +0000
commit6e368f79ecc42a60eb37b77535d35136afc2e106 (patch)
treed6ba0d9ef48069df287eed311c24f67b192da574 /src/soc/amd/sabrina/include
parent96bb0ba9e72297e98ecd2c2ce88cb4037d496ee5 (diff)
soc/amd/sabrina: Add XHCI configuration
Add xhci 2 controller support for additional USB port/ Dummy setting BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/sabrina/include')
-rw-r--r--src/soc/amd/sabrina/include/soc/pci_devs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/sabrina/include/soc/pci_devs.h b/src/soc/amd/sabrina/include/soc/pci_devs.h
index 52ecbd624b..53e4f1a910 100644
--- a/src/soc/amd/sabrina/include/soc/pci_devs.h
+++ b/src/soc/amd/sabrina/include/soc/pci_devs.h
@@ -87,6 +87,10 @@
#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)
#define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)
+#define XHCI2_DEV 0x0
+#define XHCI2_FUNC 0
+#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
+
/* SMBUS */
#define SMBUS_DEV 0x14
#define SMBUS_FUNC 0