summaryrefslogtreecommitdiff
path: root/src/soc/amd/sabrina/include
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2022-02-02 22:11:52 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-03 23:46:00 +0000
commit556d1cc17f34615e3a08ccc9a48820a304a789a8 (patch)
tree832a9c4ea64316f665dc3966a478dc44c4838e67 /src/soc/amd/sabrina/include
parentbb42f67240c7d69a8784a03565da1239908fe402 (diff)
soc/amd/*/i2c: factor out common I2C pad configuration
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/sabrina/include')
-rw-r--r--src/soc/amd/sabrina/include/soc/southbridge.h30
1 files changed, 0 insertions, 30 deletions
diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h
index e85a052a3a..e755d5019c 100644
--- a/src/soc/amd/sabrina/include/soc/southbridge.h
+++ b/src/soc/amd/sabrina/include/soc/southbridge.h
@@ -113,36 +113,6 @@
#define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */
#define BP_X48M0_S0I3_DIS BIT(4)
#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */
-#define MISC_I2C0_PAD_CTRL 0xd8
-#define MISC_I2C1_PAD_CTRL 0xdc
-#define MISC_I2C2_PAD_CTRL 0xe0
-#define MISC_I2C3_PAD_CTRL 0xe4
-#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus))
-#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-#define I2C_PAD_CTRL_NG_NORMAL 0xc
-#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5))
-#define I2C_PAD_CTRL_RX_SHIFT 4
-#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT)
-#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT)
-#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT)
-#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6)
-#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8))
-#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7
-#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9)
-#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10)
-#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */
-#define I2C_PAD_CTRL_CAP_DOWN BIT(12)
-#define I2C_PAD_CTRL_CAP_UP BIT(13)
-#define I2C_PAD_CTRL_RES_DOWN BIT(14)
-#define I2C_PAD_CTRL_RES_UP BIT(15)
-#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16)
-#define I2C_PAD_CTRL_SPARE0 BIT(17)
-#define I2C_PAD_CTRL_SPARE1 BIT(18)
-#define I2C_PAD_CTRL_PD_EN BIT(19)
-#define I2C_PAD_CTRL_COMP_SEL BIT(20)
-#define I2C_PAD_CTRL_RES_BIAS_EN BIT(21)
void fch_pre_init(void);
void fch_early_init(void);