diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-13 18:56:50 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 23:01:08 +0000 |
| commit | cbf290c692b254badb091506cc11855b52ddf266 (patch) | |
| tree | 4e2a1029a8613d97263f5ffe823e810abf90d3d3 /src/soc/amd/sabrina/Makefile.inc | |
| parent | 1c3b2a706e536c0ed11fd1d7073131fcf4a2029a (diff) | |
soc/amd/sabrina: drop CPPC code
The CPPC feature isn't available on the Sabrina SoC, so drop the
corresponding code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71a1b0717571729ebca3600ac433e621cafc4e61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/sabrina/Makefile.inc')
| -rw-r--r-- | src/soc/amd/sabrina/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index 2beb6dec77..9ee6e81a08 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -33,7 +33,6 @@ romstage-y += uart.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c ramstage-y += chip.c -ramstage-y += cppc.c ramstage-y += cpu.c ramstage-y += data_fabric.c ramstage-y += fch.c |