diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-19 22:06:11 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 23:03:43 +0000 |
| commit | ba21a1f76c363f752b82c569b787bfde3337535e (patch) | |
| tree | 1c5fd71bc444b55f60144fe74bb8fe605b43e279 /src/soc/amd/sabrina/Makefile.inc | |
| parent | cbf290c692b254badb091506cc11855b52ddf266 (diff) | |
soc/amd/sabrina: drop PM_ESPI_CS_USE_DATA2 define and eSPI util code
The Sabrina SoC doesn't have the PM_ESPI_CS_USE_DATA2 bit defined in the
PM_SPI_PAD_PU_PD register. It also doesn't have a physical LPC interface
any more, so there are no LPC pins that can be reconfigured as eSPI
interface.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I02bc8d007901c71942475fe707637c5da7227230
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/sabrina/Makefile.inc')
| -rw-r--r-- | src/soc/amd/sabrina/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index 9ee6e81a08..22ba2cc436 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -12,7 +12,6 @@ all-y += aoac.c bootblock-y += bootblock.c bootblock-y += early_fch.c -bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += reset.c |