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authorFelix Held <felix-coreboot@felixheld.de>2020-12-07 23:28:29 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-09 02:10:12 +0000
commit6b519b230e3f7d33a243b10971daff8f7228353e (patch)
treec255a05ec2b75bdcebb1bc02b1bde15a2e04fde7 /src/soc/amd/picasso
parenteb04fcbd150ce4a46239bec13f9001b836edaa0b (diff)
soc/amd: factor out PM_DECODE_EN register definitions
Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index c0a5057e2c..13ef53fc56 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -22,11 +22,6 @@
#define SMB_UART_1_8M_SHIFT 28
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
-#define PM_DECODE_EN 0x00
-#define SMBUS_ASF_IO_EN BIT(4)
-#define CF9_IO_EN BIT(1)
-#define LEGACY_IO_EN BIT(0)
-#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN in PPR */
#define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25)