diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-04 03:33:54 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-09 22:52:38 +0000 |
| commit | 649426539b73e4ada1eb0631bfa3b02be75dfd02 (patch) | |
| tree | f3bd07921d19c6e6ec2b9506e3fd9ff704df5822 /src/soc/amd/picasso | |
| parent | bd9dd420d7e0e5c2acb4073c0f4b3faec4d31ec8 (diff) | |
soc/amd/common/cpu/Kconfig: use Cxxx as CPU string for all non-CAR SoCs
Picasso already uses the Cxxx ACPI CPU device naming scheme, due to it
being what the AGESA reference code uses. We initially relied on the
AGESA/FSP generated SSDT for the P- and C-state support before we had a
native implementation for this in coreboot. The Cxxx naming scheme can
also be used for the other AMD SoCs except Stoneyridge which is pre-Zen
and doesn't select SOC_AMD_COMMON_BLOCK_NONCAR. The main advantage of
using Cxxx instead of CPxx is that the Cxxx scheme supports systems with
more than 256 CPU threads.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I884f5c0f234b5a3942dacd60847b2f095f9c0704
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73620
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9e4f0f5516..325a65a166 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -296,10 +296,6 @@ config SMM_MODULE_STACK_SIZE hex default 0x800 -config ACPI_CPU_STRING - string - default "\\_SB.C%03d" - config ACPI_BERT bool "Build ACPI BERT Table" default y |