diff options
| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:53:22 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:07:08 +0000 |
| commit | 26f97f9532933da3c1d72a7918c8a24457bbc1c0 (patch) | |
| tree | 8c25279e58ef541fae197ec193f5642a9b21b2d4 /src/soc/amd/picasso | |
| parent | 50863daef8ed75c0cb3dfd375e7622c898de5821 (diff) | |
src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fch.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/platform_descriptors.h | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index e948bca903..292cdd8318 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -29,7 +29,7 @@ Name(CRES, ResourceTemplate() { * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 63898308e7..4fcd3f71a3 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -22,7 +22,7 @@ struct __packed usb2_phy_tune { uint8_t sq_rx_tune; /* FS/LS Source Impedance Adjustment. Range 0 - 0xF */ uint8_t tx_fsls_tune; - /* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */ + /* HS Transmitter Pre-Emphasis Current Control. Range 0 - 0x3 */ uint8_t tx_pre_emp_amp_tune; /* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */ uint8_t tx_pre_emp_pulse_tune; @@ -99,7 +99,7 @@ struct soc_amd_picasso_config { * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. * For example, should we need I2C0 and I2C3 have their peripheral - * devices reseted by toggling SCL, use: + * devices reset by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 711091c5c5..44acc817ef 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -175,7 +175,7 @@ static void al2ahb_clock_gate(void) write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); } -/* configure the genral purpose PCIe clock outputs according to the devicetree settings */ +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { const struct soc_amd_picasso_config *cfg = config_of_soc(); diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 28062b689e..2ea35a940b 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -7,7 +7,7 @@ #include <platform_descriptors.h> #include <FspsUpd.h> -/* These tempory macros apply to emmc0_mode field in FSP_S_CONFIG. +/* These temporary macros apply to emmc0_mode field in FSP_S_CONFIG. * TODO: Remove when official definitions arrive. */ #define SD_DISABLE 0 #define SD_LOW_SPEED 1 |