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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-16 15:13:00 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-21 16:37:33 +0000 |
| commit | c2741855afacd073d370d47818d972cca9baba18 (patch) | |
| tree | 41522e0abfe2796935511eb92db068dc49a62a38 /src/soc/amd/picasso | |
| parent | 16562cb859ad323153a9fe6d8b3890cc7dd73093 (diff) | |
arch/x86: Rename some mainboard_romstage_entry()
These platforms use different signature for this function, so
declare them with different name to make room in global namespace.
Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/romstage.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index d8b2900fb5..c0d03d0ead 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -16,6 +16,6 @@ #ifndef __PICASSO_ROMSTAGE_H__ #define __PICASSO_ROMSTAGE_H__ -void mainboard_romstage_entry(int s3_resume); +void mainboard_romstage_entry_s3(int s3_resume); #endif /* __PICASSO_ROMSTAGE_H__ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 22b5ce4be0..7970b0edda 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -34,7 +34,7 @@ #include "chip.h" -void __weak mainboard_romstage_entry(int s3_resume) +void __weak mainboard_romstage_entry_s3(int s3_resume) { /* By default, don't do anything */ } @@ -49,7 +49,7 @@ asmlinkage void car_stage_entry(void) console_init(); - mainboard_romstage_entry(s3_resume); + mainboard_romstage_entry_s3(s3_resume); if (!s3_resume) { post_code(0x40); |