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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-09 12:37:25 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-01-26 00:17:38 +0000
commit9e591c409a3e3264f54a3784b0891a7f27dd52d8 (patch)
tree80f2cbf10a4e5fff5030ee0d4704a6cc019af01c /src/soc/amd/picasso
parentf9acd37d7f15290240d4fb9e365a7b79af57b925 (diff)
soc/amd: Refactor some ACPI S3 calls
Do not pass ACPI S3 state as a parameter, by locally calling acpi_is_wakeup_s3() compiler has better chance for optimizing HAVE_ACPI_RESUME=n case. Test for acpi_s3_allowed() is already included in the implementation of acpi_is_wakeup_s3() and is removed as redunandant. For ramstage, acpi_is_wakeup_s3() evaluates to romstage_handoff_if_resume(). Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r--src/soc/amd/picasso/romstage.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 91b316cd78..bc514561ac 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -143,14 +143,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
asmlinkage void car_stage_entry(void)
{
- int s3_resume;
-
post_code(0x40);
console_init();
- post_code(0x41);
- s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
-
post_code(0x42);
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
@@ -159,7 +154,7 @@ asmlinkage void car_stage_entry(void)
fill_chipset_state();
post_code(0x43);
- fsp_memory_init(s3_resume);
+ fsp_memory_init(acpi_is_wakeup_s3());
soc_update_mrc_cache();
memmap_stash_early_dram_usage();