diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-11-30 18:18:35 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-02 21:27:03 +0000 |
| commit | 6443ad4a53ab65a2a9c1d29f422644e450c04cd7 (patch) | |
| tree | 4843082fa04ab74fd08b53aa01eb65165e8edb4f /src/soc/amd/picasso | |
| parent | 5b3831c75abe5fc50739984eaa70fbada2575bb7 (diff) | |
soc/amd: factor out common AOAC device enable and status query functions
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.
Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/aoac.c | 34 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/picasso/uart.c | 1 |
4 files changed, 2 insertions, 37 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 7f32c3cc98..e2feebd98e 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_PCI diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index 21031f7d5f..7fd839bf46 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -30,40 +30,6 @@ const static unsigned int aoac_devs[] = { FCH_AOAC_DEV_ESPI, }; -void power_on_aoac_device(unsigned int dev) -{ - uint8_t byte; - - /* Power on the UART and AMBA devices */ - byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); - byte |= FCH_AOAC_PWR_ON_DEV; - byte &= ~FCH_AOAC_TARGET_DEVICE_STATE; - byte |= FCH_AOAC_D0_INITIALIZED; - aoac_write8(AOAC_DEV_D3_CTL(dev), byte); -} - -void power_off_aoac_device(unsigned int dev) -{ - uint8_t byte; - - /* Power off the UART and AMBA devices */ - byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); - byte &= ~FCH_AOAC_PWR_ON_DEV; - aoac_write8(AOAC_DEV_D3_CTL(dev), byte); -} - -bool is_aoac_device_enabled(unsigned int dev) -{ - uint8_t byte; - - byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); - byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); - if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) - return true; - else - return false; -} - void wait_for_aoac_enabled(unsigned int dev) { while (!is_aoac_device_enabled(dev)) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 8a2ae49b3f..809eb97486 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -247,9 +247,6 @@ typedef struct aoac_devs { } __packed aoac_devs_t; void enable_aoac_devices(void); -bool is_aoac_device_enabled(unsigned int dev); -void power_on_aoac_device(unsigned int dev); -void power_off_aoac_device(unsigned int dev); void wait_for_aoac_enabled(unsigned int dev); void sb_clk_output_48Mhz(void); void sb_enable(struct device *dev); diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 1aa42ef47b..a71a0e97d9 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -6,6 +6,7 @@ #include <device/mmio.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <soc/southbridge.h> #include <soc/gpio.h> #include <soc/uart.h> |