diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-18 19:18:21 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-29 15:49:54 +0000 |
| commit | 39bd46f4a4f3c1cc76f1007f82050c943fd09bb5 (patch) | |
| tree | a3f3aa4016b8ac0793ed5bccd7c5b26ed474592d /src/soc/amd/picasso | |
| parent | 9f6622fb5588a9322b7f1c71bc198d0c2e1dd1bf (diff) | |
soc/amd/common: Drop ACPIMMIO GPIO bank separation
The banks are one after each other in the ACPIMMIO space. Also
there is space for more banks and existing ASL takes advantage
of the property.
Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42522
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/acpi.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/picasso/i2c.c | 23 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/i2c.h | 5 |
3 files changed, 10 insertions, 22 deletions
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index c868c3458a..75509eb4c1 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -302,7 +302,7 @@ static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); return -1; } - uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); + uintptr_t addr = gpio_get_address(gpio_num); acpigen_soc_get_gpio_in_local5(addr); @@ -332,7 +332,7 @@ static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); return -1; } - uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); + uintptr_t addr = gpio_get_address(gpio_num); /* Store (0x40, Local0) */ acpigen_write_store(); diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 6f34573aa9..881278f254 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -154,23 +154,16 @@ static const struct soc_amd_gpio i2c_2_gpi[] = { static void save_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { - uint32_t *gpio_ptr; - - gpio_ptr = (uint32_t *)gpio_get_address(gpio); save_table->mux_value = iomux_read8(gpio); - save_table->control_value = read32(gpio_ptr); + save_table->control_value = gpio_read32(gpio); } static void restore_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { - uint32_t *gpio_ptr; - - gpio_ptr = (uint32_t *)gpio_get_address(gpio); iomux_write8(gpio, save_table->mux_value); iomux_read8(gpio); - write32(gpio_ptr, save_table->control_value); - read32(gpio_ptr); + gpio_write32_rb(gpio, save_table->control_value); } /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ @@ -196,19 +189,19 @@ void sb_reset_i2c_slaves(void) */ for (j = 0; j < 9; j++) { if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); + gpio_write32(I2C2_SCL_PIN, GPIO_OUTPUT_ENABLE); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); + gpio_write32(I2C3_SCL_PIN, GPIO_OUTPUT_ENABLE); - read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + gpio_read32(0); /* Flush posted write */ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); + gpio_write32(I2C2_SCL_PIN, 0); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); + gpio_write32(I2C3_SCL_PIN, 0); - read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + gpio_read32(0); /* Flush posted write */ udelay(4); } diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 58c27a424d..34c19aaf29 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -17,11 +17,6 @@ struct soc_amd_i2c_save { #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19 -#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) -#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) -#define GPIO_SCL_HIGH 0 -#define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE - #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx |