diff options
author | Raul E Rangel <rrangel@chromium.org> | 2021-02-12 14:37:43 -0700 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-14 18:05:17 +0000 |
commit | 394c6b092251f0da8f0bd159e0eb08a41a6e4afc (patch) | |
tree | e9d347574e889fc911ebe512d2bfc012239a5d73 /src/soc/amd/picasso | |
parent | 844775059d8cb456dec988e6378f3a73ea730001 (diff) |
soc/amd: Move update_microcode.c to common/block/cpu
We also want to support uCode loading on cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r-- | src/soc/amd/picasso/Kconfig | 5 | ||||
-rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/amd/picasso/update_microcode.c | 90 |
3 files changed, 4 insertions, 92 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d037d48990..16a12972b4 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART + select SOC_AMD_COMMON_BLOCK_UCODE select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -58,7 +59,9 @@ config CPU_SPECIFIC_OPTIONS select FSP_COMPRESS_FSP_S_LZMA select UDK_2017_BINDING select HAVE_CF9_RESET - select SUPPORT_CPU_UCODE_IN_CBFS + +config SOC_AMD_COMMON_BLOCK_UCODE_SIZE + default 3200 config FSP_M_FILE string "FSP-M (memory init) binary path and filename" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 99e2da1040..d2a5e4c393 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -48,7 +48,6 @@ ramstage-y += uart.c ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += fsp_params.c -ramstage-y += update_microcode.c ramstage-y += graphics.c ramstage-y += pcie_gpp.c ramstage-y += xhci.c diff --git a/src/soc/amd/picasso/update_microcode.c b/src/soc/amd/picasso/update_microcode.c deleted file mode 100644 index 47a98353b9..0000000000 --- a/src/soc/amd/picasso/update_microcode.c +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <cpu/amd/microcode.h> -#include <commonlib/helpers.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <cbfs.h> - -#define MPB_MAX_SIZE 3200 -#define MPB_DATA_OFFSET 32 - -struct microcode { - uint32_t date_code; - uint32_t patch_id; - - uint16_t mc_patch_data_id; - uint8_t reserved1[6]; - - uint32_t chipset1_dev_id; - uint32_t chipset2_dev_id; - - uint16_t processor_rev_id; - - uint8_t chipset1_rev_id; - uint8_t chipset2_rev_id; - - uint8_t reserved2[4]; - - uint8_t m_patch_data[MPB_MAX_SIZE-MPB_DATA_OFFSET]; -} __packed; - -static void apply_microcode_patch(const struct microcode *m) -{ - uint32_t new_patch_id; - msr_t msr; - - msr.hi = (uint64_t)(uintptr_t)m >> 32; - msr.lo = (uintptr_t)m & 0xffffffff; - - wrmsr(MSR_PATCH_LOADER, msr); - - printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", - m->patch_id); - - msr = rdmsr(MSR_PATCH_LEVEL); - new_patch_id = msr.lo; - - if (new_patch_id == m->patch_id) - printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n", - new_patch_id); - else - printk(BIOS_ERR, "microcode: being updated to patch id = 0x%08x failed\n", - new_patch_id); -} - -static uint16_t get_equivalent_processor_rev_id(void) -{ - uint32_t cpuid_family = cpuid_eax(1); - - return (uint16_t)((cpuid_family & 0xff0000) >> 8 | (cpuid_family & 0xff)); -} - -static void amd_update_microcode(const void *ucode, size_t ucode_len, - uint16_t equivalent_processor_rev_id) -{ - const struct microcode *m; - - for (m = (struct microcode *)ucode; - m < (struct microcode *)ucode + ucode_len/MPB_MAX_SIZE; m++) { - if (m->processor_rev_id == equivalent_processor_rev_id) - apply_microcode_patch(m); - } -} - -void amd_update_microcode_from_cbfs(void) -{ - const void *ucode; - size_t ucode_len; - uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id(); - - ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len); - if (!ucode) { - printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n"); - return; - } - - amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); -} |