soc/amd: factor out common family 17h&19h TSC and monotonic timer code

The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the
code.

Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

4 files changed, 1 insertions, 74 deletions

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 2ac1235fcf..79fc3be621 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -24,10 +24,7 @@ config CPU_SPECIFIC_OPTIONS
 	select IOAPIC
 	select HAVE_EM100_SUPPORT
 	select HAVE_USBDEBUG_OPTIONS
-	select COLLECT_TIMESTAMPS_NO_TSC
 	select SOC_AMD_COMMON_BLOCK_SPI
-	select TSC_SYNC_LFENCE
-	select UDELAY_TSC
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_NONCAR
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
@@ -44,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
 	select SOC_AMD_COMMON_BLOCK_SMU
+	select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
 	select PROVIDES_ROM_SHARING
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index c77278337e..d86d97e7e2 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -3,7 +3,6 @@
 ifeq ($(CONFIG_SOC_AMD_PICASSO),y)
 
 subdirs-y += ../../../cpu/amd/mtrr/
-subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/x86/lapic
 subdirs-y += ../../../cpu/x86/cache
 subdirs-y += ../../../cpu/x86/mtrr
@@ -17,8 +16,6 @@ bootblock-y += southbridge.c
 bootblock-y += i2c.c
 bootblock-y += uart.c
 bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
-bootblock-y += monotonic_timer.c
-bootblock-y += tsc_freq.c
 bootblock-y += gpio.c
 bootblock-y += config.c
 bootblock-y += reset.c
@@ -30,8 +27,6 @@ romstage-y += reset.c
 romstage-y += memmap.c
 romstage-y += uart.c
 romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
-romstage-y += monotonic_timer.c
-romstage-y += tsc_freq.c
 romstage-y += aoac.c
 romstage-y += southbridge.c
 romstage-y += psp.c
@@ -44,8 +39,6 @@ verstage-y += aoac.c
 verstage_x86-y += gpio.c
 verstage_x86-y += uart.c
 verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
-verstage_x86-y += monotonic_timer.c
-verstage_x86-y += tsc_freq.c
 verstage_x86-y += reset.c
 
 ramstage-y += i2c.c
@@ -66,8 +59,6 @@ ramstage-y += memmap.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-y += uart.c
 ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
-ramstage-y += monotonic_timer.c
-ramstage-y += tsc_freq.c
 ramstage-y += finalize.c
 ramstage-y += soc_util.c
 ramstage-y += psp.c
@@ -80,8 +71,6 @@ ramstage-y += xhci.c
 ramstage-y += dmi.c
 
 smm-y += smihandler.c
-smm-y += monotonic_timer.c
-smm-y += tsc_freq.c
 ifeq ($(CONFIG_DEBUG_SMI),y)
 smm-y += uart.c
 smm-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
diff --git a/src/soc/amd/picasso/monotonic_timer.c b/src/soc/amd/picasso/monotonic_timer.c
deleted file mode 100644
index 941532cca6..0000000000
--- a/src/soc/amd/picasso/monotonic_timer.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include <timer.h>
-#include <timestamp.h>
-
-void timer_monotonic_get(struct mono_time *mt)
-{
-	mono_time_set_usecs(mt, timestamp_get());
-}
-
-uint64_t timestamp_get(void)
-{
-	return rdtscll() / tsc_freq_mhz();
-}
diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c
deleted file mode 100644
index 55c86653ce..0000000000
--- a/src/soc/amd/picasso/tsc_freq.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/tsc.h>
-#include <console/console.h>
-
-static unsigned long mhz;
-
-/* Use this default TSC frequency when it can not be correctly calculated.
-   Higher numbers are safer as it will result in longer delays using TSC */
-#define TSC_DEFAULT_FREQ_MHZ	4000
-
-unsigned long tsc_freq_mhz(void)
-{
-	msr_t msr;
-	uint8_t cpufid;
-	uint8_t cpudid;
-	uint8_t high_state;
-
-	if (mhz)
-		return mhz;
-
-	high_state = rdmsr(PS_LIM_REG).lo & 0x7;
-	msr = rdmsr(PSTATE_0_MSR + high_state);
-	if (!(msr.hi & 0x80000000))
-		die("Unknown error: cannot determine P-state 0\n");
-
-	cpufid = (msr.lo & 0xff);
-	cpudid = (msr.lo & 0x3f00) >> 8;
-
-	/* normally core frequency is calculated as (fid * 25) / (did / 8) */
-	if (!cpudid) {
-		mhz = TSC_DEFAULT_FREQ_MHZ;
-		printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz);
-	} else if ((cpudid >= 8) && (cpudid <= 0x30)) {
-		mhz = (200 * cpufid) / cpudid;
-	} else {
-		mhz = 25 * cpufid;
-		printk(BIOS_ERR, "Invalid frequency divisor 0x%x, assume 1\n", cpudid);
-	}
-
-	return mhz;
-}