diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-22 18:16:39 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-15 19:34:10 +0000 |
| commit | 8c1e603800d8403bf16ea6bb247eb7793fc063d0 (patch) | |
| tree | 3c75608681cd99850f3ccc00c849dd04a9985bad /src/soc/amd/picasso | |
| parent | 79d0ea4b7eb201ff8dda3e21240e74662bfa285e (diff) | |
soc/amd/common,picasso: Place some ENV_X86 guards
Base address symbols for ACPIMMIO banks that would not get
assigned at runtime must not resolve at linker-stage either.
The build of PSP-verstage should pass without the preprocessor
macros that have x86-centric view of memory space.
Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 43e56582a1..0296c87dd8 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -3,6 +3,8 @@ #ifndef AMD_PICASSO_IOMAP_H #define AMD_PICASSO_IOMAP_H +#if ENV_X86 + /* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ #define GNB_IO_APIC_ADDR 0xfec01000 @@ -22,6 +24,8 @@ /* Reserved 0xfecd1000-0xfedc3fff */ +#endif /* ENV_X86 */ + /* * Picasso/Dali have I2C0 and I2C1 wired to the Sensor Fusion Hub (SFH/MP2). * The controllers are not directly accessible via the x86. @@ -37,6 +41,8 @@ #define I2C_MASTER_START_INDEX 2 #define I2C_SLAVE_DEV_COUNT 1 +#if ENV_X86 + #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 @@ -62,6 +68,8 @@ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) +#endif /* ENV_X86 */ + /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 #define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE |