soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resources

Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the
legacy PCI config space access is needed on all AMD SoCs, implement a
common add_pci_cfg_resources function that reports both and gets called
from amd_pci_domain_read_resources and don't report those in the SoC-
specific code any more. The only functional change is that on Genoa now
the IO ports used for the legacy PCI config space access get reserved.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 0 insertions, 4 deletions

diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c
index ffe4f66f5b..1e702ab8e5 100644
--- a/src/soc/amd/picasso/root_complex.c
+++ b/src/soc/amd/picasso/root_complex.c
@@ -111,8 +111,6 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	early_reserved_dram_start = e->base;
 	early_reserved_dram_end = e->base + e->size;
 
-	fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
-
 	/* 0x0 - 0x9ffff */
 	ram_range(dev, (*idx)++, 0, 0xa0000);
 
@@ -132,8 +130,6 @@ void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 	 * cbmem_top() accounts for low UMA and TSEG if they are used. */
 	ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
 
-	mmconf_resource(dev, (*idx)++);
-
 	/* Reserve fixed IOMMU MMIO region */
 	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);