diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-10-05 14:47:00 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-14 20:19:46 +0000 |
| commit | 7f7b01d46747e0147cac4427a2667dd6bf213a91 (patch) | |
| tree | f591bcdc478a0e488b19773fff36d39c70f5cf41 /src/soc/amd/picasso | |
| parent | b3dcb96dc57ade665306e9c03f41353fd11737aa (diff) | |
soc/amd/sata.c: Hook up directly in devicetree
Cezanne has two SATA controllers, but doesn't select
SOC_AMD_COMMON_BLOCK_SATA, so it's not added to the SATA devices in the
Cezanne chipset devicetree.
Change-Id: If7f0a9638151cf981d891464a2c3a0ec5fc9c780
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/chipset.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index b4479d7cc1..ab286de864 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -30,7 +30,7 @@ chip soc/amd/picasso end device pci 08.2 alias internal_bridge_b off # internal bridge to bus B ops amd_internal_pcie_gpp_ops - device pci 0.0 alias sata off end + device pci 0.0 alias sata off ops amd_sata_ops end device pci 0.1 alias xgbe_0 off end device pci 0.2 alias xgbe_1 off end end |