diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-04-09 11:50:48 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-10 20:22:27 +0000 |
| commit | 65b0afe9a687aebeed70eccd78e1ad99b96bc8bc (patch) | |
| tree | de861f60afbb85cc5b49f0ff5334b4120f3683ba /src/soc/amd/picasso | |
| parent | 6ada39e790a4f7ea2e5d1b74a27c2e7b68a6115d (diff) | |
soc/amd/cezanne: Add GRXS and GTXS method
Add GRXS and GTXS support. Move the gpio method into common place.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi.c | 47 |
2 files changed, 1 insertions, 47 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index b6ab78494a..765ed600c6 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 7315b924a1..b879571163 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -364,50 +364,3 @@ void generate_cpu_entries(const struct device *device) acpigen_write_name_integer("PCNT", logical_cores); acpigen_pop_len(); } - -static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - /* op (gpio_num) */ - acpigen_emit_namestring(op); - acpigen_write_integer(gpio_num); - return 0; -} - -static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - /* Store (op (gpio_num), Local0) */ - acpigen_write_store(); - acpigen_soc_gpio_op(op, gpio_num); - acpigen_emit_byte(LOCAL0_OP); - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.GRXS", gpio_num); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.GTXS", gpio_num); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.STXS", gpio_num); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.CTXS", gpio_num); -} |