diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-03 17:54:56 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-06 16:03:31 +0000 |
| commit | 4b679b06480e5897c6120b8e72ea755c57af2593 (patch) | |
| tree | 5c2894edd5299588cee6585387e0303f18fb4afb /src/soc/amd/picasso | |
| parent | cc34162734b4d924012102210095bcf8903ea758 (diff) | |
soc/amd/picasso/acpi: don't announce unimplemented duty cycle control
Picasso neither has the corresponding P_CNT register implemented nor
writes a _PTC ACPI object that would specify the P_CNT register. The
Picasso UEFI reference code also sets the duty_width FADT entry to 0.
This also aligns the Picasso code with the Cezanne code in this regard.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I74645e5c4e54a2ad6bc7f9e72f5f656027a79860
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/acpi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 89ca50260f..7244a1186e 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -86,8 +86,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ - fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ + fadt->duty_offset = 0; /* Not supported */ + fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ |