soc/amd/picasso: remove broken and unused legacy UART support

The UARTs in the Picasso SoC are memory mapped, but there is also some
hardware support that isn't used by any board to make the UARTs behave
like the ones found on legacy x86 machines from the 90s.

In the MMIO mode the MMIO address of the UART controller is passed to
the OS via ACPI. The OS expects the base clock of the UART controller to
be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and
drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It
is also possible to enable additional decodes from four 8 byte legacy
I/O locations used for serial ports to the different UART controllers,
which doesn't disable the MMIO access though. The legacy I/O-mapped
serial ports are usually expected to have a base clock of 16*115200Hz
which the hardware can also provide to the UART's baud rate generator.
So there are two possible valid configurations to use the UARTs; either
MMIO access in combination with a 48MHz base clock or the legacy I/O
decode with a ~1.8MHz base clock.

The existing code unconditionally generates ACPI objects for all enabled
UARTs, so those shouldn't be put into legacy mode and switching the base
clock to ~1.8MHz was only done in the case that the UART was used as
coreboot console UART which still used the MMIO access, but the lower
base clock. Since no board even selects this option and it's rather
invasive to properly implement this feature, just drop the corresponding
broken code.

TEST=SoC UART console still works on Mandolin.

Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 57 deletions

diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c
index b417051b97..472a0be7d5 100644
--- a/src/soc/amd/picasso/uart.c
+++ b/src/soc/amd/picasso/uart.c
@@ -5,7 +5,6 @@
 #include <commonlib/helpers.h>
 #include <device/mmio.h>
 #include <amdblocks/gpio_banks.h>
-#include <amdblocks/acpimmio.h>
 #include <amdblocks/aoac.h>
 #include <soc/southbridge.h>
 #include <soc/gpio.h>
@@ -42,71 +41,17 @@ uintptr_t get_uart_base(unsigned int idx)
 	return uart_info[idx].base;
 }
 
-static bool get_uart_idx(uintptr_t base, unsigned int *idx)
-{
-	for (unsigned int i = 0; i < ARRAY_SIZE(uart_info); i++) {
-		if (base == uart_info[i].base) {
-			*idx = i;
-			return true;
-		}
-	}
-
-	return false;
-}
-
 void clear_uart_legacy_config(void)
 {
 	write16((void *)FCH_LEGACY_UART_DECODE, 0);
 }
 
-void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx)
-{
-	uint16_t uart_legacy_decode;
-	uint8_t uart_map_offset;
-
-	if (uart_idx >= ARRAY_SIZE(uart_info) || range_idx >= ARRAY_SIZE(uart_info))
-		return;
-
-	uart_legacy_decode = read16((void *)FCH_LEGACY_UART_DECODE);
-	/* Map uart_idx to io range_idx */
-	uart_map_offset = range_idx * FCH_LEGACY_UART_MAP_SIZE + FCH_LEGACY_UART_MAP_SHIFT;
-	uart_legacy_decode &= ~(FCH_LEGACY_UART_MAP_MASK << uart_map_offset);
-	uart_legacy_decode |= uart_idx << uart_map_offset;
-	/* Enable io range */
-	uart_legacy_decode |= 1 << range_idx;
-	write16((void *)FCH_LEGACY_UART_DECODE, uart_legacy_decode);
-}
-
-static void enable_uart_legacy_decode(uintptr_t base)
-{
-	unsigned int idx;
-	const uint8_t range_idx[ARRAY_SIZE(uart_info)] = {
-		FCH_LEGACY_UART_RANGE_3F8,
-		FCH_LEGACY_UART_RANGE_2F8,
-		FCH_LEGACY_UART_RANGE_3E8,
-		FCH_LEGACY_UART_RANGE_2E8,
-	};
-
-	if (get_uart_idx(base, &idx)) {
-		set_uart_legacy_config(idx, range_idx[idx]);
-	}
-}
-
 void set_uart_config(unsigned int idx)
 {
-	uint32_t uart_ctrl;
-
 	if (idx >= ARRAY_SIZE(uart_info))
 		return;
 
 	program_gpios(uart_info[idx].mux, 2);
-
-	if (CONFIG(AMD_SOC_UART_1_8MZ)) {
-		uart_ctrl = sm_pci_read32(SMB_UART_CONFIG);
-		uart_ctrl |= 1 << (SMB_UART_1_8M_SHIFT + idx);
-		sm_pci_write32(SMB_UART_CONFIG, uart_ctrl);
-	}
-
 }
 
 static const char *uart_acpi_name(const struct device *dev)
@@ -151,8 +96,6 @@ static void uart_enable(struct device *dev)
 	if (dev->enabled) {
 		power_on_aoac_device(dev_id);
 		wait_for_aoac_enabled(dev_id);
-		if (CONFIG(AMD_SOC_UART_LEGACY))
-			enable_uart_legacy_decode(dev->path.mmio.addr);
 	} else {
 		power_off_aoac_device(dev_id);
 	}