soc/amd/picasso: Reduce 48M out configuration

Picasso has only a single 48M output.  Simplify the setup function.
Note that while the feature is similar to older products, the register
definition and Enable bit has changed.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 2 insertions, 16 deletions

diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 84c15a7595..e1d16b7e3c 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -190,26 +190,12 @@ static void sb_enable_legacy_io(void)
 	pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN);
 }
 
-void sb_clk_output_48Mhz(u32 osc)
+void sb_clk_output_48Mhz(void)
 {
 	u32 ctrl;
 
-	/*
-	 * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M)
-	 * or OSCOUT2 (USBCLK/25M_48M_OSC).  The frequency defaults to 48MHz.
-	 */
 	ctrl = misc_read32(MISC_CLK_CNTL1);
-
-	switch (osc) {
-	case 1:
-		ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
-		break;
-	case 2:
-		ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB;
-		break;
-	default:
-		return; /* do nothing if invalid */
-	}
+	ctrl |= BP_X48M0_OUTPUT_EN;
 	misc_write32(MISC_CLK_CNTL1, ctrl);
 }