aboutsummaryrefslogtreecommitdiff
path: root/src/soc/amd/picasso/southbridge.c
diff options
context:
space:
mode:
authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-06-13 16:03:47 -0600
committerMartin Roth <martinroth@google.com>2019-07-06 18:21:39 +0000
commit78025f6c5c8a65d662c3af7d8de2ad5a59752419 (patch)
tree7e8a577d9cd4aa0716cfe8976c585491079dcf51 /src/soc/amd/picasso/southbridge.c
parentfcfa35670a191d2313324fb313bac237e7a3d0c6 (diff)
soc/amd/picasso: Remove all AGESA references
Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove all source, support functions, and comments related to AGESA. Family 17h requires v9 which has no similarities to v5 for integration into a host firmware. AGESA v9 support will be added via subsequent patches into the appropriate locations. Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/southbridge.c')
-rw-r--r--src/soc/amd/picasso/southbridge.c56
1 files changed, 0 insertions, 56 deletions
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 87b933e119..84c15a7595 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -23,7 +23,6 @@
#include <device/pci_ops.h>
#include <cbmem.h>
#include <amdblocks/amd_pci_util.h>
-#include <amdblocks/agesawrapper.h>
#include <amdblocks/reset.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/lpc.h>
@@ -34,7 +33,6 @@
#include <soc/amd_pci_int_defs.h>
#include <delay.h>
#include <soc/pci_devs.h>
-#include <agesa_headers.h>
#include <soc/nvs.h>
#include <types.h>
@@ -54,60 +52,6 @@ const static struct picasso_aoac aoac_devs[] = {
{ FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 }
};
-static int is_sata_config(void)
-{
- return !((SataNativeIde == CONFIG_PICASSO_SATA_MODE)
- || (SataLegacyIde == CONFIG_PICASSO_SATA_MODE));
-}
-
-static inline int sb_sata_enable(void)
-{
- /* True if IDE or AHCI. */
- return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) ||
- (SataAhci == CONFIG_PICASSO_SATA_MODE);
-}
-
-static inline int sb_ide_enable(void)
-{
- /* True if IDE or LEGACY IDE. */
- return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) ||
- (SataLegacyIde == CONFIG_PICASSO_SATA_MODE);
-}
-
-void SetFchResetParams(FCH_RESET_INTERFACE *params)
-{
- const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
- if (dev && dev->enabled) {
- params->SataEnable = sb_sata_enable();
- params->IdeEnable = sb_ide_enable();
- } else {
- params->SataEnable = FALSE;
- params->IdeEnable = FALSE;
- }
-}
-
-void SetFchEnvParams(FCH_INTERFACE *params)
-{
- const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
- params->AzaliaController = AzEnable;
- params->SataClass = CONFIG_PICASSO_SATA_MODE;
- if (dev && dev->enabled) {
- params->SataEnable = is_sata_config();
- params->IdeEnable = !params->SataEnable;
- params->SataIdeMode = (CONFIG_PICASSO_SATA_MODE ==
- SataLegacyIde);
- } else {
- params->SataEnable = FALSE;
- params->IdeEnable = FALSE;
- params->SataIdeMode = FALSE;
- }
-}
-
-void SetFchMidParams(FCH_INTERFACE *params)
-{
- SetFchEnvParams(params);
-}
-
/*
* Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
* provides a visible association with the index, therefore helping