diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-11 12:34:04 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-03 21:41:04 +0000 |
| commit | 19ea0169108dc2eff743ae640a8108eb5852612d (patch) | |
| tree | 90a9e0463572f14ae900b631495e7d55c26d61da /src/soc/amd/picasso/southbridge.c | |
| parent | 7e5a2660bc927adac1fc420f94c111b8f8aae191 (diff) | |
soc/amd/picasso: Remove most stoneyridge USB
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove
source that uses these. Remove USB devices from the AOAC registers.
Remove the D0/D3 support from ASL, including all supporting xHCI
firmware loading support. Remove xHCI firmware from amdfw.rom.
Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/picasso/southbridge.c')
| -rw-r--r-- | src/soc/amd/picasso/southbridge.c | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 711ebc592a..dca3591f85 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -77,7 +77,6 @@ static inline int sb_ide_enable(void) void SetFchResetParams(FCH_RESET_INTERFACE *params) { const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); if (dev && dev->enabled) { params->SataEnable = sb_sata_enable(); params->IdeEnable = sb_ide_enable(); @@ -579,10 +578,6 @@ void southbridge_init(void *chip_info) static void set_sb_final_nvs(void) { - uintptr_t amdfw_rom; - uintptr_t xhci_fw; - uintptr_t fwaddr; - size_t fwsize; const struct device *sd, *sata; struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); @@ -595,29 +590,12 @@ static void set_sb_final_nvs(void) gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); - gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); - gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; sata = pcidev_path_on_root(SATA_DEVFN); gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; - - amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); - xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); - - fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - gnvs->fw00 = 0; - gnvs->fw01 = ((32 * KiB) << 16) + 0; - gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; - gnvs->fw03 = fwsize << 16; - - gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) - & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } void southbridge_final(void *chip_info) |