soc/amd/picasso: Create picasso as a copy of stoneyridge

So that everyone can see what's being updated from stoney, we're
starting with a direct copy of the stoney directory. There are
arguments both for and against doing it this way, but I believe
This the most transparent way.  We've moved much of the duplicated
stoney code into the soc/amd/common directory and will continue
that work as it becomes obvious that we have unchanged code between
the SOCs.

Makefile.inc has been renamed as makefile.inc so that it won't
build in jenkins until the directory is  updated.

Other than that change, this is an exact copy of the stoneyridge
SOC directory which will be updated in the follow-on commits in
the patch train.

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 191 insertions, 0 deletions

diff --git a/src/soc/amd/picasso/smbus.c b/src/soc/amd/picasso/smbus.c
new file mode 100644
index 0000000000..31457f98b8
--- /dev/null
+++ b/src/soc/amd/picasso/smbus.c
@@ -0,0 +1,191 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <stdint.h>
+#include <console/console.h>
+#include <amdblocks/acpimmio.h>
+#include <soc/smbus.h>
+#include <soc/southbridge.h>
+
+static u8 controller_read8(u32 base, u8 reg)
+{
+	switch (base) {
+	case ACPIMMIO_SMBUS_BASE:
+		return smbus_read8(reg);
+	case ACPIMMIO_ASF_BASE:
+		return asf_read8(reg);
+	default:
+		printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n",
+				base);
+	}
+	return 0xff;
+}
+
+static void controller_write8(u32 base, u8 reg, u8 val)
+{
+	switch (base) {
+	case ACPIMMIO_SMBUS_BASE:
+		smbus_write8(reg, val);
+		break;
+	case ACPIMMIO_ASF_BASE:
+		asf_write8(reg, val);
+		break;
+	default:
+		printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n",
+				base);
+	}
+}
+
+static int smbus_wait_until_ready(u32 mmio)
+{
+	u32 loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+		val = controller_read8(mmio, SMBHSTSTAT);
+		val &= SMBHST_STAT_VAL_BITS;
+		if (val == 0) {	/* ready now */
+			return 0;
+		}
+		controller_write8(mmio, SMBHSTSTAT, val);
+	} while (--loops);
+	return -2;		/* time out */
+}
+
+static int smbus_wait_until_done(u32 mmio)
+{
+	u32 loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+
+		val = controller_read8(mmio, SMBHSTSTAT);
+		val &= SMBHST_STAT_VAL_BITS;	/* mask off reserved bits */
+		if (val & SMBHST_STAT_ERROR_BITS)
+			return -5;	/* error */
+		if (val == SMBHST_STAT_NOERROR) {
+			controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */
+			return 0;
+		}
+	} while (--loops);
+	return -3;		/* timeout */
+}
+
+int do_smbus_recv_byte(u32 mmio, u8 device)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(mmio) < 0)
+		return -2;	/* not ready */
+
+	/* set the device I'm talking to */
+	controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
+
+	byte = controller_read8(mmio, SMBHSTCTRL);
+	byte &= ~SMBHST_CTRL_MODE_BITS;			/* Clear [4:2] */
+	byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW;	/* set mode, start */
+	controller_write8(mmio, SMBHSTCTRL, byte);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(mmio) < 0)
+		return -3;	/* timeout or error */
+
+	/* read results of transaction */
+	byte = controller_read8(mmio, SMBHSTDAT0);
+
+	return byte;
+}
+
+int do_smbus_send_byte(u32 mmio, u8 device, u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(mmio) < 0)
+		return -2;	/* not ready */
+
+	/* set the command... */
+	controller_write8(mmio, SMBHSTDAT0, val);
+
+	/* set the device I'm talking to */
+	controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
+
+	byte = controller_read8(mmio, SMBHSTCTRL);
+	byte &= ~SMBHST_CTRL_MODE_BITS;			/* Clear [4:2] */
+	byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW;	/* set mode, start */
+	controller_write8(mmio, SMBHSTCTRL, byte);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(mmio) < 0)
+		return -3;	/* timeout or error */
+
+	return 0;
+}
+
+int do_smbus_read_byte(u32 mmio, u8 device, u8 address)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(mmio) < 0)
+		return -2;	/* not ready */
+
+	/* set the command/address... */
+	controller_write8(mmio, SMBHSTCMD, address & 0xff);
+
+	/* set the device I'm talking to */
+	controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
+
+	byte = controller_read8(mmio, SMBHSTCTRL);
+	byte &= ~SMBHST_CTRL_MODE_BITS;			/* Clear [4:2] */
+	byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW;	/* set mode, start */
+	controller_write8(mmio, SMBHSTCTRL, byte);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(mmio) < 0)
+		return -3;	/* timeout or error */
+
+	/* read results of transaction */
+	byte = controller_read8(mmio, SMBHSTDAT0);
+
+	return byte;
+}
+
+int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(mmio) < 0)
+		return -2;	/* not ready */
+
+	/* set the command/address... */
+	controller_write8(mmio, SMBHSTCMD, address & 0xff);
+
+	/* set the device I'm talking to */
+	controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
+
+	/* output value */
+	controller_write8(mmio, SMBHSTDAT0, val);
+
+	byte = controller_read8(mmio, SMBHSTCTRL);
+	byte &= ~SMBHST_CTRL_MODE_BITS;			/* Clear [4:2] */
+	byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW;	/* set mode, start */
+	controller_write8(mmio, SMBHSTCTRL, byte);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(mmio) < 0)
+		return -3;	/* timeout or error */
+
+	return 0;
+}