soc/amd/picasso: Create picasso as a copy of stoneyridge

So that everyone can see what's being updated from stoney, we're
starting with a direct copy of the stoney directory. There are
arguments both for and against doing it this way, but I believe
This the most transparent way.  We've moved much of the duplicated
stoney code into the soc/amd/common directory and will continue
that work as it becomes obvious that we have unchanged code between
the SOCs.

Makefile.inc has been renamed as makefile.inc so that it won't
build in jenkins until the directory is  updated.

Other than that change, this is an exact copy of the stoneyridge
SOC directory which will be updated in the follow-on commits in
the patch train.

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 104 insertions, 0 deletions

diff --git a/src/soc/amd/picasso/sm.c b/src/soc/amd/picasso/sm.c
new file mode 100644
index 0000000000..803e628320
--- /dev/null
+++ b/src/soc/amd/picasso/sm.c
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/smbus.h>
+#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
+#include <stdlib.h>
+#include <soc/southbridge.h>
+#include <soc/smbus.h>
+
+/*
+* The southbridge enables all USB controllers by default in SMBUS Control.
+* The southbridge enables SATA by default in SMBUS Control.
+*/
+
+static void sm_init(struct device *dev)
+{
+	setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
+}
+
+static u32 get_sm_mmio(struct device *dev)
+{
+	struct resource *res;
+	struct bus *pbus;
+
+	pbus = get_pbus_smbus(dev);
+	res = find_resource(pbus->dev, 0x90);
+	if (res->base == SMB_BASE_ADDR)
+		return ACPIMMIO_SMBUS_BASE;
+
+	return ACPIMMIO_ASF_BASE;
+}
+
+static int lsmbus_recv_byte(struct device *dev)
+{
+	u8 device;
+
+	device = dev->path.i2c.device;
+	return do_smbus_recv_byte(get_sm_mmio(dev), device);
+}
+
+static int lsmbus_send_byte(struct device *dev, u8 val)
+{
+	u8 device;
+
+	device = dev->path.i2c.device;
+	return do_smbus_send_byte(get_sm_mmio(dev), device, val);
+}
+
+static int lsmbus_read_byte(struct device *dev, u8 address)
+{
+	u8 device;
+
+	device = dev->path.i2c.device;
+	return do_smbus_read_byte(get_sm_mmio(dev), device, address);
+}
+
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
+{
+	u8 device;
+
+	device = dev->path.i2c.device;
+	return do_smbus_write_byte(get_sm_mmio(dev), device, address, val);
+}
+static struct smbus_bus_operations lops_smbus_bus = {
+	.recv_byte = lsmbus_recv_byte,
+	.send_byte = lsmbus_send_byte,
+	.read_byte = lsmbus_read_byte,
+	.write_byte = lsmbus_write_byte,
+};
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+static struct device_operations smbus_ops = {
+	.read_resources = DEVICE_NOOP,
+	.set_resources = DEVICE_NOOP,
+	.enable_resources = pci_dev_enable_resources,
+	.init = sm_init,
+	.scan_bus = scan_smbus,
+	.ops_pci = &lops_pci,
+	.ops_smbus_bus = &lops_smbus_bus,
+};
+static const struct pci_driver smbus_driver __pci_driver = {
+	.ops = &smbus_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_CZ_SMBUS,
+};