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author | Felix Held <felix-coreboot@felixheld.de> | 2024-01-31 12:17:58 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-02 20:40:20 +0000 |
commit | 416cc665929e4e66bcab3e395daa031401a61fe8 (patch) | |
tree | 33a0ea5ec6151cd1f4b876ca2091ff9d07eb4b07 /src/soc/amd/picasso/sata.c | |
parent | 0b76f02892ba37eceff4340c2ca8c4da3f721f9f (diff) |
soc/amd: commonize PCI root IOAPIC initialization
Make the initialization of the IOAPIC(s) in the PCI root(s) common
across all AMD family 17h+ SoCs. For this the more general
implementation from the Genoa code that supports multiple PC roots is
moved to the common AMD code. All other family 17h+ SoCs are then
adapted to use the common code. For those non-Genoa SoCs, the
initialization of this second IOAPIC is moved from the northbridge
device to the domain device above to match Genoa.
Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized
on Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80286
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/sata.c')
0 files changed, 0 insertions, 0 deletions