soc/amd/picasso: Create picasso as a copy of stoneyridge

So that everyone can see what's being updated from stoney, we're
starting with a direct copy of the stoney directory. There are
arguments both for and against doing it this way, but I believe
This the most transparent way.  We've moved much of the duplicated
stoney code into the soc/amd/common directory and will continue
that work as it becomes obvious that we have unchanged code between
the SOCs.

Makefile.inc has been renamed as makefile.inc so that it won't
build in jenkins until the directory is  updated.

Other than that change, this is an exact copy of the stoneyridge
SOC directory which will be updated in the follow-on commits in
the patch train.

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 48 insertions, 0 deletions

diff --git a/src/soc/amd/picasso/sata.c b/src/soc/amd/picasso/sata.c
new file mode 100644
index 0000000000..6740698dd2
--- /dev/null
+++ b/src/soc/amd/picasso/sata.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
+#include <amdblocks/sata.h>
+#include <soc/southbridge.h>
+
+void soc_enable_sata_features(struct device *dev)
+{
+	u8 *ahci_ptr;
+	u32 misc_ctl, cap_cfg;
+
+	u32 temp;
+
+	/* unlock the write-protect */
+	misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
+	misc_ctl |= SATA_MISC_SUBCLASS_WREN;
+	pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl);
+
+	/* set the SATA AHCI mode to allow port expanders */
+	ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN(
+		pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256);
+
+	cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG);
+	cap_cfg |= SATA_CAPABILITY_SPM;
+	write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg);
+
+	/* lock the write-protect */
+	temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
+	temp &= ~SATA_MISC_SUBCLASS_WREN;
+	pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp);
+};