diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2020-06-05 09:51:30 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-08 19:08:03 +0000 |
| commit | e80a1b1690d9d70e14cd7aa0b99fa317ac33b4e4 (patch) | |
| tree | 6c85666cdbbcd5701de823666d8d00a2903a0475 /src/soc/amd/picasso/romstage.c | |
| parent | d6161d46ff9563154f5c46509c0498ed11b16607 (diff) | |
soc/amd/picasso: remove save/restore MTRRs around FSP-M
AGESA FSP-M implementation is now not updating MTRRs out from
under the caller. As such, remove the save/restore of MTRRs
from the FSP-M call.
BUG=b:155426691
Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/picasso/romstage.c')
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 0bbceec0d1..35d2aa2b46 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -12,7 +12,6 @@ #include <program_loading.h> #include <elog.h> #include <soc/romstage.h> -#include <soc/mtrr.h> #include <types.h> #include "chip.h" #include <fsp/api.h> @@ -22,16 +21,6 @@ void __weak mainboard_romstage_entry_s3(int s3_resume) /* By default, don't do anything */ } -/* TODO(b/155426691): Make FSP AGESA leave MTRRs alone */ -static void clear_agesa_mtrrs(void) -{ - disable_cache(); - - picasso_restore_mtrrs(); - - enable_cache(); -} - void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -95,15 +84,9 @@ asmlinkage void car_stage_entry(void) printk(BIOS_DEBUG, "Family_Model: %08x\n", val); post_code(0x43); - picasso_save_mtrrs(); - - post_code(0x44); fsp_memory_init(s3_resume); - post_code(0x45); - clear_agesa_mtrrs(); - - post_code(0x46); + post_code(0x44); run_ramstage(); post_code(0x50); /* Should never see this post code. */ |