diff options
| author | Martin Roth <martin@coreboot.org> | 2020-06-26 08:40:56 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-24 09:23:05 +0000 |
| commit | 0c12abe4625e9bde9b31cbd9b1b9e2727bdee715 (patch) | |
| tree | 14213cb2b460d2ebc4a2abf9a8ee01a0d9c0de82 /src/soc/amd/picasso/memlayout_x86.ld | |
| parent | 3818d03fa2dcc5be891b909df9f1581296b458ef (diff) | |
soc/amd/picasso: Add console & timestamp buffers to psp_verstage
Create areas for console & timestamp data in psp_verstage and pass it to
the x86 to save for use later.
BUG=b:159220781
TEST=Build & Boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I41c8d7a1565e761187e941d7d6021805a9744d06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/memlayout_x86.ld')
| -rw-r--r-- | src/soc/amd/picasso/memlayout_x86.ld | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/picasso/memlayout_x86.ld index 6f43ba18af..7930793275 100644 --- a/src/soc/amd/picasso/memlayout_x86.ld +++ b/src/soc/amd/picasso/memlayout_x86.ld @@ -2,6 +2,7 @@ #include <memlayout.h> #include <arch/header.ld> +#include <soc/psp_transfer.h> #define EARLY_RESERVED_DRAM_START(addr) SYMBOL(early_reserved_dram, addr) #define EARLY_RESERVED_DRAM_END(addr) SYMBOL(eearly_reserved_dram, addr) @@ -38,14 +39,16 @@ * | Unused hole | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE * | Preram CBMEM console | * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + PSP_SHAREDMEM_SIZE * | PSP shared (vboot workbuf) | * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + * | Transfer Info Structure | * +--------------------------------+ PSP_SHAREDMEM_BASE * | APOB (64KiB) | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS @@ -72,14 +75,18 @@ SECTIONS #if CONFIG(VBOOT) PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE) + _transfer_buffer = .; + REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) - TIMESTAMP(., 0x200) + TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) FMAP_CACHE(., FMAP_SIZE) - +#if CONFIG(VBOOT) + _etransfer_buffer = .; +#endif _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) |