diff options
author | Martin Roth <martin@coreboot.org> | 2020-05-28 00:44:50 -0600 |
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committer | Martin Roth <martinroth@google.com> | 2020-07-08 19:34:59 +0000 |
commit | c7acf1666a517f0fcfec3a5f64791932ca145c45 (patch) | |
tree | 8f2e6c0539a028ee3f2e27e5c80fe613678e7444 /src/soc/amd/picasso/memlayout_psp_verstage.ld | |
parent | ac41f582351dc2c6aaaf0c1ef662e6d99b67b4ce (diff) |
soc/amd/picasso: add psp_verstage
This is the main code for building coreboot's verstage as a userspace
application to run on the PSP. It does a minimal setup of hardware,
then runs verstage_main. It uses hardware hashing to increase the speed
and will directly reboot into recovery mode if there are any failures.
BUG=b:158124527
TEST=Build & boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/memlayout_psp_verstage.ld')
-rw-r--r-- | src/soc/amd/picasso/memlayout_psp_verstage.ld | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/picasso/memlayout_psp_verstage.ld new file mode 100644 index 0000000000..d2b409c850 --- /dev/null +++ b/src/soc/amd/picasso/memlayout_psp_verstage.ld @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> + +/* + * Start of available space is 0x15000 and this is where the + * header for the user app (verstage) must be mapped. + * Size is 0x28000 bytes + */ +#define PSP_SRAM_START 0x15000 +#define PSP_SRAM_SIZE 160K + +#define VERSTAGE_START 0x15000 +#define VERSTAGE_SIZE 60K +#define VBOOT_WORK_START VERSTAGE_START + VERSTAGE_SIZE +#define VBOOT_WORK_SIZE 12K +#define FMAP_CACHE_SIZE 2K + +/* + * The temp stack can be made much smaller if needed - even 256 bytes + * should be sufficient. This is just for the function mapping the + * actual stack. + */ +#define PSP_VERSTAGE_TEMP_STACK_START 0x39000 +#define PSP_VERSTAGE_TEMP_STACK_SIZE 4K + +/* + * The top of the stack must be 4k aligned, so set the bottom as 4k aligned + * and make the size a multiple of 4k + */ +#define PSP_VERSTAGE_STACK_START 0x3B000 +#define PSP_VERSTAGE_STACK_SIZE 8K + +ENTRY(_psp_vs_start) +SECTIONS +{ + SRAM_START(PSP_SRAM_START) + _verstage = .; + + .text : { *(PSP_HEADER_DATA) } + .text : { *(.text._psp_vs_start) } + .text : { *(.text.Main) } + .text : { *(.text*) } + .rodata : { *(.rodata*) } + + .data : { *(.data*) } + .data : { *(PSP_FOOTER_DATA) } + + _bss_start = .; + .bss : { *(.bss*) } + _bss_end = .; + + _everstage = _verstage + VERSTAGE_SIZE; + + REGION(vboot2_work, VBOOT_WORK_START, VBOOT_WORK_SIZE, 64) + + FMAP_CACHE(., FMAP_SIZE) + + PSP_VERSTAGE_TEMP_STACK_END = (PSP_VERSTAGE_TEMP_STACK_START + PSP_VERSTAGE_TEMP_STACK_SIZE ); + + REGION(stack, PSP_VERSTAGE_STACK_START, PSP_VERSTAGE_STACK_SIZE, 64) + PSP_VERSTAGE_STACK_BASE = _stack; + PSP_VERSTAGE_STACK_END = _estack; + SRAM_END(PSP_SRAM_START + PSP_SRAM_SIZE) +} |