diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2020-11-21 02:12:54 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-22 17:35:20 +0000 |
commit | 9065f4f8ed2facb60df3f4906b8e1e66e8958379 (patch) | |
tree | 8cc5ad648509e03a4bf4bc7e2f4e08ba1b982cd3 /src/soc/amd/picasso/memlayout_psp_verstage.ld | |
parent | 53ed3e501f4744b4dd42c1418819a5546fe4f0cf (diff) |
soc/amd: move non-CAR linker scripts to common directory
AMD family 17h and newer don't use cache as RAM, since the RAM is
already initialized by the PSP when the x86 cores are released from
reset. Therefore they use a different linker script as the rest of the
x86 chips in coreboot do. Since there will be support for newer
generations than Picasso will be added, move those linker scripts from
soc/amd/picasso to soc/amd/common/block/cpu/noncar.
TEST=Timeless build of amd/mandolin and amd/gardenia result in identical
binaries.
Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/memlayout_psp_verstage.ld')
-rw-r--r-- | src/soc/amd/picasso/memlayout_psp_verstage.ld | 62 |
1 files changed, 0 insertions, 62 deletions
diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/picasso/memlayout_psp_verstage.ld deleted file mode 100644 index ca95cf81bd..0000000000 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <memlayout.h> -#include <soc/psp_transfer.h> -#include <fmap_config.h> - -/* - * Start of available space is 0x15000 and this is where the - * header for the user app (verstage) must be mapped. - * Size is 0x28000 bytes - */ -#define PSP_SRAM_START 0x15000 -#define PSP_SRAM_SIZE 160K - -#define VERSTAGE_START 0x15000 - -/* - * The temp stack can be made much smaller if needed - even 256 bytes - * should be sufficient. This is just for the function mapping the - * actual stack. - */ -#define PSP_VERSTAGE_TEMP_STACK_START 0x32000 -#define PSP_VERSTAGE_TEMP_STACK_SIZE 4K - -/* - * The top of the stack must be 4k aligned, so set the bottom as 4k aligned - * and make the size a multiple of 4k - */ -#define PSP_VERSTAGE_STACK_START 0x33000 -#define PSP_VERSTAGE_STACK_SIZE 40K - -ENTRY(_psp_vs_start) -SECTIONS -{ - SRAM_START(PSP_SRAM_START) - _verstage = .; - - .text : { *(PSP_HEADER_DATA) } - .text : { *(.text._psp_vs_start) } - .text : { *(.text.Main) } - .text : { *(.text*) } - .rodata : { *(.rodata*) } - - .data : { *(.data*) } - .data : { *(PSP_FOOTER_DATA) } - - _bss_start = .; - .bss : { *(.bss*) } - _bss_end = .; - - ALIGN_COUNTER(64) - _everstage = .; - - #include "memlayout_transfer_buffer.inc" - - PSP_VERSTAGE_TEMP_STACK_END = (PSP_VERSTAGE_TEMP_STACK_START + PSP_VERSTAGE_TEMP_STACK_SIZE ); - - REGION(stack, PSP_VERSTAGE_STACK_START, PSP_VERSTAGE_STACK_SIZE, 64) - PSP_VERSTAGE_STACK_BASE = _stack; - PSP_VERSTAGE_STACK_END = _estack; - SRAM_END(PSP_SRAM_START + PSP_SRAM_SIZE) -} |