soc/amd/picasso: Place early stages and data buffers at the bottom of DRAM

This change updates memlayout.ld for Picasso to place all early
stages (bootblock, romstage, FSP-M, verstage) and data buffers (vboot
workbuf, APOB, preram-cbmem console, timestamp, early BSP stack) at
the bottom of DRAM starting at 32MiB. This uses static allocation for
most components by defining Kconfig variables for base and size. It
relies on the linker to complain if any of the assumptions are broken.

This also allows romstage to use linker symbols for
_early_reserved_dram and _eearly_reserved_dram to store information in
CBMEM about the early DRAM usage by coreboot before ramstage starts
execution. This allows ramstage to reserve this memory region in BIOS
tables so that S3 resume can reuse the same space without corrupting
OS memory.

BUG=b:155322763
TEST=Verified memory reported by coreboot:
Writing coreboot table at 0xcc656000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-0000000001ffffff: RAM
 4. 0000000002000000-000000000223ffff: RESERVED
 5. 0000000002240000-00000000cc512fff: RAM
 6. 00000000cc513000-00000000cc6bffff: CONFIGURATION TABLES
 7. 00000000cc6c0000-00000000cc7c7fff: RAMSTAGE
 8. 00000000cc7c8000-00000000cd7fffff: CONFIGURATION TABLES
 9. 00000000cd800000-00000000cfffffff: RESERVED
10. 00000000f8000000-00000000fbffffff: RESERVED
11. 0000000100000000-000000042f33ffff: RAM
12. 000000042f340000-000000042fffffff: RESERVED

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I009e1ea71b5b5a8e65eba16911897b2586ccfdb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

1 files changed, 84 insertions, 29 deletions

diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld
index 8b2390909e..a82e303dad 100644
--- a/src/soc/amd/picasso/memlayout.ld
+++ b/src/soc/amd/picasso/memlayout.ld
@@ -3,39 +3,94 @@
 #include <memlayout.h>
 #include <arch/header.ld>
 
-#define EARLY_MEMLAYOUT	"src/arch/x86/early_ram.ld"
+#define EARLY_RESERVED_DRAM_START(addr)		SYMBOL(early_reserved_dram, addr)
+#define EARLY_RESERVED_DRAM_END(addr)		SYMBOL(eearly_reserved_dram, addr)
 
+#define PSP_SHAREDMEM_DRAM_START(addr)		SYMBOL(psp_sharedmem_dram, addr)
+#define PSP_SHAREDMEM_DRAM_END(addr)		SYMBOL(epsp_sharedmem_dram, addr)
+
+/*
+ *
+ *                     +--------------------------------+
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *                     |                                |
+ *   reserved_dram_end +--------------------------------+
+ *                     |                                |
+ *                     |       verstage (if reqd)       |
+ *                     |          (VERSTAGE_SIZE)       |
+ *                     +--------------------------------+ VERSTAGE_ADDR
+ *                     |                                |
+ *                     |            FSP-M               |
+ *                     |         (FSP_M_SIZE)           |
+ *                     +--------------------------------+ FSP_M_ADDR
+ *                     |                                |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
+ *                     |           romstage             |
+ *                     |        (ROMSTAGE_SIZE)         |
+ *                     +--------------------------------+ ROMSTAGE_ADDR
+ *                     |           bootblock            |
+ *                     |     (C_ENV_BOOTBLOCK_SIZE)     |
+ *                     +--------------------------------+ BOOTBLOCK_ADDR
+ *                     |          Unused hole           |
+ *                     +--------------------------------+
+ *                     |     FMAP cache (FMAP_SIZE)     |
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
+ *                     |  Early Timestamp region (512B) |
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
+ *                     |      Preram CBMEM console      |
+ *                     |   (PRERAM_CBMEM_CONSOLE_SIZE)  |
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
+ *                     |   PSP shared (vboot workbuf)   |
+ *                     |      (PSP_SHAREDMEM_SIZE)      |
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE
+ *                     |          APOB (64KiB)          |
+ *                     +--------------------------------+ PSP_APOB_DRAM_ADDRESS
+ *                     |        Early BSP stack         |
+ *                     |   (EARLYRAM_BSP_STACK_SIZE)    |
+ * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
+ *                     |              DRAM              |
+ *                     +--------------------------------+ 0x100000
+ *                     |           Option ROM           |
+ *                     +--------------------------------+ 0xc0000
+ *                     |           Legacy VGA           |
+ *                     +--------------------------------+ 0xa0000
+ *                     |              DRAM              |
+ *                     +--------------------------------+ 0x0
+ */
 SECTIONS
 {
-	/*
-	 * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
-	 * like other architectures/chipsets it's not possible because of
-	 * the linking games played during romstage creation by trying
-	 * to find the final landing place in CBFS for XIP. Therefore,
-	 * conditionalize with macros.
-	 */
-#if ENV_RAMSTAGE
-	RAMSTAGE(CONFIG_RAMBASE, (CONFIG(RELOCATABLE_RAMSTAGE) ? 8M :
-					CONFIG_RAMTOP - CONFIG_RAMBASE))
-
-#elif ENV_ROMSTAGE
-	/* The 1M size is not allocated. It's just for basic size checking.
-	 * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
-	ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)
-
-	#include EARLY_MEMLAYOUT
-#elif ENV_SEPARATE_VERSTAGE
-	/* The 1M size is not allocated. It's just for basic size checking.
-	 * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
-	VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M)
-
-	#include EARLY_MEMLAYOUT
-#elif ENV_BOOTBLOCK
-	BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10,
-			CONFIG_C_ENV_BOOTBLOCK_SIZE)
-
-	#include EARLY_MEMLAYOUT
+	DRAM_START(0x0)
+
+	EARLY_RESERVED_DRAM_START(CONFIG_EARLY_RESERVED_DRAM_BASE)
+
+	EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE)
+	REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, 64K, 1)
+
+#if CONFIG(VBOOT)
+	PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE)
+	VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE)
+	PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE)
 #endif
+
+	PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
+	TIMESTAMP(., 0x200)
+	FMAP_CACHE(., FMAP_SIZE)
+
+	_ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock");
+	BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE)
+	ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE)
+	REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1)
+#if CONFIG(VBOOT_SEPARATE_VERSTAGE)
+	VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
+#endif
+
+	EARLY_RESERVED_DRAM_END(.)
+
+	RAMSTAGE(CONFIG_RAMBASE, 8M)
 }
 
 #if ENV_BOOTBLOCK