diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-20 10:29:29 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-10-20 16:42:09 +0000 |
| commit | c0b8d0d5b5bd3f43e607ee317447d0a27fb5d474 (patch) | |
| tree | 58f8e86bd3c5336c161b6caf57ecd530a4cd9684 /src/soc/amd/picasso/include | |
| parent | 0d441daef6e7ca4d43360058b960ccab8d2d21b5 (diff) | |
soc/amd/picasso: Update UARTs
Add a function to uart.c to ensure the right IOMux settings are
programmed for the console UART. Update Kconfig to reflect the
new addresses.
Give the user the ability to downclock the UARTs' refclock to
1.8342MHz.
Add the abiltiy to use an APU UART at a legacy I/O address.
Update the AOAC register configuration for the two additional
UARTs.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 7 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 20 |
2 files changed, 24 insertions, 3 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index ad0e7c4609..344b8865ed 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -28,6 +28,7 @@ * any documentation but should be considered reserved through FED8_1FFFh. */ #include <amdblocks/acpimmio_map.h> +#define SUPPORTS_ACPIMMIO_SM_PCI_BASE 1 /* 0xfed80000 */ #define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ #define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ #define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ @@ -60,8 +61,10 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -#define APU_UART0_BASE 0xfedc6000 -#define APU_UART1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 +#define APU_UART2_BASE 0xfedce000 +#define APU_UART3_BASE 0xfedcf000 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 8bd061b2fc..0fb187dc52 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -28,6 +28,14 @@ * - fixed addresses offset from 0xfed80000 */ +/* SMBus controller registers: 0xfed80000 or D14F0 */ +#define SMB_UART_CONFIG 0xfc +#define SMB_UART3_1_8M BIT(31) /* defaults are 0 = 48MHz */ +#define SMB_UART2_1_8M BIT(30) +#define SMB_UART1_1_8M BIT(29) +#define SMB_UART0_1_8M BIT(28) +#define SMB_UART_1_8M_SHIFT 28 + /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PM_DECODE_EN 0x00 #define SMBUS_ASF_IO_EN BIT(4) @@ -209,6 +217,7 @@ #define FCH_AOAC_DEV_UART1 12 #define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 /* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ @@ -230,6 +239,11 @@ #define FCH_AOAC_STAT0 BIT(6) #define FCH_AOAC_STAT1 BIT(7) +#define FCH_UART_LEGACY_DECODE 0xfedc0020 +#define FCH_LEGACY_3F8_SH 3 +#define FCH_LEGACY_2F8_SH 1 +#define FCH_LEGACY_3E8_SH 2 + #define PM1_LIMIT 16 #define GPE0_LIMIT 28 #define TOTAL_BITS(a) (8 * sizeof(a)) @@ -294,7 +308,10 @@ typedef struct aoac_devs { unsigned int :1; unsigned int ut0e:1; /* 11: UART0 */ unsigned int ut1e:1; /* 12: UART1 */ - unsigned int :14; + unsigned int :3; + unsigned int ut2e:1; /* 16: UART2 */ + unsigned int :9; + unsigned int ut3e:1; /* 26: UART3 */ unsigned int espi:1; /* 27: ESPI */ unsigned int :4; } __packed aoac_devs_t; @@ -317,6 +334,7 @@ void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void fch_pre_init(void); void fch_early_init(void); +void set_uart_config(int idx); /** * @brief Save the UMA bize * |