diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-11 12:18:20 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-03 21:30:16 +0000 |
| commit | bc4c903c1f0bbf5297309082f31cfc2f70addb99 (patch) | |
| tree | 99924f3d876aad0b7d56dfd974ece168c5028c9f /src/soc/amd/picasso/include | |
| parent | 30cf1551683810504f7823e42d4cb6515459cff8 (diff) | |
soc/amd/picasso: Change all remaining soc names
Convert all remaining stoneyridge names to picasso.
Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/acpi.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/cpu.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 12 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 2 |
4 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 71fe10eb26..f141a05714 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -20,7 +20,7 @@ #include <arch/acpi.h> -#if CONFIG(STONEYRIDGE_LEGACY_FREE) +#if CONFIG(PICASSO_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index d9d48ad27c..7d4764567a 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -29,7 +29,7 @@ #define SOC_EARLY_VMTRR_CAR_HEAP 2 #define SOC_EARLY_VMTRR_TEMPRAM 3 -void stoney_init_cpus(struct device *dev); +void picasso_init_cpus(struct device *dev); void check_mca(void); #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index a63b16462b..7e2b7fc2f6 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -61,16 +61,16 @@ /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 -#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE -#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE +#define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ -#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ -#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x08) /* 6 bytes */ +#define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x18) /* 4 bytes */ #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index fa9206e33a..7ba179fbea 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -316,7 +316,7 @@ #define RST_CMD BIT(2) #define SYS_RST BIT(1) -struct stoneyridge_aoac { +struct picasso_aoac { int enable; int status; }; |