diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-20 11:03:06 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-09 20:23:50 +0000 |
| commit | 0bd0806d2f8158cf43f52fc3106fc759bd6c4a94 (patch) | |
| tree | 398a4c744b0018b6f8fc58c67cd43bd23842ec97 /src/soc/amd/picasso/include | |
| parent | ad1fdac9879eb0aba5d7f05752ae010f3bdcff66 (diff) | |
soc/amd/picasso: Reduce 48M out configuration
Picasso has only a single 48M output. Simplify the setup function.
Note that while the feature is similar to older products, the register
definition and Enable bit has changed.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 36880a14a3..8c96aa7f99 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -175,6 +175,7 @@ #define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) #define MISC_CLK_CNTL1 0x40 #define CG1PLL_FBDIV_TEST BIT(26) +#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ @@ -312,7 +313,7 @@ struct soc_power_reg { }; void enable_aoac_devices(void); -void sb_clk_output_48Mhz(u32 osc); +void sb_clk_output_48Mhz(void); void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); |