diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-06-30 18:26:35 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-03 21:46:18 +0000 |
| commit | fa4a74b098731bf3e0979c20a65fa883bf4c57f3 (patch) | |
| tree | a3d7fafa4213e7652f7c8a1fdcd6e4c87d2a0b6c /src/soc/amd/picasso/include | |
| parent | 19ea0169108dc2eff743ae640a8108eb5852612d (diff) | |
soc/amd/picasso: Add xhci1 and remove ehci
Change-Id: I9d0098082c224bbf5ab2b4f0f41eb8b5b729eec7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/pci_devs.h | 26 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 4 |
2 files changed, 15 insertions, 15 deletions
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 478a2cb623..c823fdbfdc 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -151,12 +151,19 @@ #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) -/* XHCI */ -#define XHCI_DEV 0x10 -#define XHCI_FUNC 0 -#define XHCI_DEVID 0x7914 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) -#define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC) +/* USB 3.1 */ +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVID 0x15e0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) +#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) + +/* USB 3.1 */ +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVID 0x15e1 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) +#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) /* SATA */ #define SATA_DEV 0x11 @@ -167,13 +174,6 @@ #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) -/* EHCI */ -#define EHCI_DEV 0x12 -#define EHCI_FUNC 0 -#define EHCI_DEVID 0x7908 -#define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC) -#define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC) - /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index a5892bbd87..4392e4f099 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -367,8 +367,8 @@ uint64_t get_uma_base(void); * over current support. */ #define USB_OC_DISABLE_ALL 0xffff -int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map); -int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map); +int mainboard_get_xhci0_oc_map(uint16_t *usb_oc_map); +int mainboard_get_xhci1_oc_map(uint16_t *usb_oc_map); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); |